Anu Gupta
VIDWAN ID: 228401

Prof Anu Gupta

Female Doctor of Philosophy
Professor | Department of Electrical and Electronics engineering
Birla Institute of Technology & Sciences, Pilani
Rajasthan
Expertise: Electrical and Electronic Engineering
83 Publications
0 Projects
518 Scopus Citations
404 CrossRef
31 Years 8 Months Total Experience
Publications
83 Total
Articles
30
Books
3
Chapters
2
Proceedings
48
Activity

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Scopus Scopus
518 Citations
11 h-index
CrossRef CrossRef
404 Citations
10 h-index
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Personal Details

Doctor of Philosophy
2005
Central Institute of Post Harvest Engineering and Technology
Professor
Jan 1995 – Present
Birla Institute of Technology & Sciences, Pilani | Department of Electrical and Electronics engineering
Engineering and Technology
Electrical and Electronic Engineering

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Scholarly Work

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Iris localization in lris recognition system : algorithms and hardware implemention

University Birla Institute of Technology and Science Pilani
Year 2016
Downloads 0

Low- power high- speed and compact ternary VLSI circuit designs using carbon nanotube field effect transistors

University Birla Institute of Technology and Science Pilani
Year 2015
Downloads 0

Low-Power High-Speed and Compact Ternary VLSI Circuit Designs using Carbon Nanotube Field Effect Transistors

University BITS-PILANI
Year 2016
Downloads 0

Architectural Exploration And Design of low power Memory And Arithmetic Circuit Using Subthreshold Design Technique

University BITS-PILANI
Year 2017
Downloads 0

A PORTABLE REAL-TIME COLORIMETRIC DETECTION DEVICE AND METHOD OF USING THE SAME

Birla Institute Of Technology & Science (BITS)
Pilani
- Application No. : 202111017453 Filed : 14-04-2021
Published : 24-02-2023 Filed

Scholarly Publications

Accurate iris localization using edge map generation and adaptive circular hough transform for less constrained iris images

Open Access
Journal Article
International Journal of Electrical and Computer Engineering (IJECE). Year: 2016. Volume: 6 , Issue: 4 , Pages: 1637 .
Authors: Kumar, V.; Asati, A.; Gupta, A.

Power-aware design of logarithmic prefix adders in subthreshold regime: A comparative analysis

Open Access
Conference Paper
Procedia Computer Science. Year: 2015. Volume: 46 , Pages: 1401-1408 .
Authors: Gupta, P.; Gupta, A.; Asati, A.

Hardware-efficient low-power 2-bit ternary ALU design in CNTFET technology

Journal Article
International Journal of Electronics. Year: 2016. Pages: 1-15 .
Authors: Murotiya, S.L.; Gupta, A.

Iris localization based on integro-differential operator for unconstrained infrared iris images

Conference Paper
Year: 2016. Pages: 277-281 .
Authors: Kumar, V.; Asati, A.; Gupta, A.

A low power low noise amplifier for biomedical applications

Conference Paper
Year: 2015. Pages: 1-6 .
Authors: Dubey, D.; Gupta, A.

CNTFET-based design of dynamic ternary full adder cell

Conference Paper
Year: 2015. Pages: 1-5 .
Authors: Murotiya, S.L.; Gupta, A.; Vasishth, S.

Design and ASIC implementation of column compression Wallace/Dadda multiplier in sub-threshold regime

Conference Paper
Year: 2015.
Authors: Gupta, P.; Gupta, A.; Samnani, D.; Asati, A.

Design and performance evaluation of a low transistor ternary CNTFET SRAM cell

Conference Paper
Year: 2015. Pages: 38-43 .
Authors: Srinivasan, P.; Bhat, A.S.; Murotiya, S.L.; Gupta, A.
Showing 73 to 80 of 83 publications