Nithin Kumar Y B
VIDWAN ID: 141239

Dr Nithin Kumar Y B

Male Doctor of Philosophy
Associate Professor | Department of Electronics and Communication Engineering
National Institute of Technology Goa
Goa
Expertise: Electrical and Electronic Engineering
97 Publications
0 Projects
1140 Scopus Citations
902 CrossRef
12 Years 9 Months Total Experience
Publications
97 Total
Articles
34
Books
1
Proceedings
62
Activity

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Scopus Scopus
1,140 Citations
17 h-index
CrossRef CrossRef
902 Citations
15 h-index
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Personal Details

Doctor of Philosophy
2013
Indian Institute of Technology, Ropar
Associate Professor
Dec 2013 – Present
National Institute of Technology Goa | Department of Electronics and Communication Engineering
Engineering and Technology
Electrical and Electronic Engineering

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Scholarly Publications

A 0.9 V Configurable Dual Mode Comparator using a Supply Boosting Technique

Conference Paper
Year: 2025.
Authors: Sourabh Mestry; Siddharth R. K; Nithin Kumar Y. B; Vasantha M. H; Edoardo Bonizzoni

Training of Generative Adversarial Networks using Particle Swarm Optimization Algorithm

Conference Paper
Year: 2021. Pages: 127-130 .
Authors: K.G. Shreeharsha; Charudatta G. Korde; M. H. Vasantha; Y. B. Nithin Kumar

On The Design Of Rationalised Bi-orthogonal Wavelet Using Reversible Logic

Conference Paper
Year: 2022. Volume: 2022-May , Pages: 3428-3432 .
Authors: Sithara Raveendran; Pranose J. Edavoor; Y. B. Nithin Kumar; M. H. Vasantha

A 11-ns, 3.85-fJ, Deep Sub-threshold, Energy Efficient Level Shifter in 65-nm CMOS

Conference Paper
Year: 2023. Volume: 2023-May .
Authors: Rathod Balaji; R.K. Siddharth; Sanmitra Naik; Y.B. Nithin Kumar; M.H. Vasantha; Edoardo Bonizzoni

A 2.5 GHz, 1-Kb SRAM with Auxiliary Circuit Assisted Sense Amplifier in 65-nm CMOS Process

Conference Paper
Year: 2023. Volume: 2023-January , Pages: 115-120 .
Authors: Rupesh D. Kadhao; Siddharth R. K.; Nithin Kumar Y. B.; Vasantha M. H.; Devesh Dwivedi

Approximate Three-Operand Binary Adder for Error-Resilient Applications

Conference Paper
Year: 2023. Pages: 287-291 .
Authors: Darshan Halliyavar; Siddharth R. K.; Vasantha M. H.; Nithin Kumar Y. B.; Sithara R.

Power Saving Scheme for Process Corner Calibrated Standard Cell Based Flash ADC in Wireless Surveillance Applications

Journal Article
SN Computer Science. Year: 2020. Volume: 1 , Issue: 6 .
Authors: R. K. Siddharth; Y. B. Nithin Kumar; M. H. Vasantha

Power Reduction of a Level Triggered D Flip-Flop using Clock Gating and Power Gating Techniques

Conference Paper
Year: 2024. Pages: 99-103 .
Authors: Yamana Ashok Kumar; Nithin Kumar Y.B; Vasantha M.H; Siddharth R.K.
Showing 1 to 8 of 97 publications