Vidwan-ID : 228428

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Academic

Orcid Id 0000-0002-4914-5951
Scopus Id 26435667800
Researcher Id AAC-3674-2019
Google Scholar Id h_dycmkAAAAJ

Score criteria

Criteria	Point
Personal Details	1
Expertise Details	1
Experience Details	1
Qualification Details	1
Employee ID	0.2
Orcid ID	0.2
Researcher ID	0.2
Scopus ID	0.2
Google Scholar ID	0.2
Honours <=3< /td>	0.3
Honours >3	0.5
Project worth less than Rs.5,00,000/-	0.2
Project worth more than Rs.5,00,000/-	0.5
Membership in professional Bodies < 5	0.5
Membership in professional bodies >=5	1
No of publications <=15	1
No of publications between 15-45	2
No of publications >45	3

Vidwan Score 8.4

45 Articles

4 Books

3 Projects

3 Awards

Prof Abhijit Rameshwar Asati

Professor

Birla Institute of Technology and Science, Pilani

Publications

45

Journal Articles
4

Book
34

Conference
Proceedings
3

Projects
3

Awards
6
1
56

Citations / H-Index

262 Citations

10 h-index

190 Citations

Altmetrics

Google Scholar

Co-author Network

Expertise

Electrical and Electronic Engineering

(a)VLSI design, Micro/ Nano electronics, VLSI test, CAD for VLSI (b) Embedded system design, high level synthesis (c) Hardware development for image processing applications (d) Artificial intelligence and machine learning applications (e) Artificial intelligence and machine learning hardware design etc. (f) Cryptography

Personal Information

Prof Abhijit Rameshwar Asati

1974 Male

Birla Institute Of Technology And Science, Pilani Birla Institute Of Technology And Science, Pilani, Vidya Vihar

Pilani, Rajasthan, India - 333031

Experience

2002 - Present

Professor

Department of Electrical and Electronics engineering

Birla Institute of Technology and Science, Pilani, Jhunjhunu

Qualification

2010

Ph.D

Birla Institute of Technology and Science, Pilani

Honours and Awards

2018

Senior member IEEE

IEEE

2010

Biography Published

Who's Who

2002

project completion award

Intel

2018

Senior member IEEE

IEEE

2010

Biography Published

Who's Who

2002

project completion award

Intel

Read Less

Doctoral Theses Guided

2022

Methodologies for Area, Speed, and Power Optimizations in High-Level Synthesis for Diverse Applications

BITS Pilani,Prateek Sikka

2018

Design Exploration of Low Power Arithmetic and SRAM Circuits using Subthreshold Design Technique

Birla Institute of Technology and Science Pilani,Priya Gupta

2017

Iris Localization in Iris Recognition System: Algorithms and Hardware Implementation

Birla Institute of Technology and Science Pilani,Vineet Kumar

2022

Methodologies for Area, Speed, and Power Optimizations in High-Level Synthesis for Diverse Applications

BITS Pilani,Prateek Sikka

2018

Design Exploration of Low Power Arithmetic and SRAM Circuits using Subthreshold Design Technique

Birla Institute of Technology and Science Pilani,Priya Gupta

2017

Iris Localization in Iris Recognition System: Algorithms and Hardware Implementation

Birla Institute of Technology and Science Pilani,Vineet Kumar

2017

Framework for Translation of C/C++ Applications on Reconfigurable Computing Systems

Birla Institute of Technology and Science Pilani,Ashish Mishra

Read Less

Membership In Committees

2018

IEEE

Senior Member

2015

IEEE

Memebr

2014

IETE

Life Member

2018

IEEE

Senior Member

2015

IEEE

Memebr

2014

IETE

Life Member

2014

Institution of Engineers India

Life Member

2012

'Metrology Society of India

Life Member

Read Less

Research Projects

Convolutional neural networks and their Hardware Implementation for Improved Performance.

Funding Agency : DST

RTL to GSDII flow and DFT implementation

Funding Agency : Cypress Semiconductor Ltd. Bangalore

Unsigned binary division circuit using non-restoring division method

Funding Agency : Intel

Convolutional neural networks and their Hardware Implementation for Improved Performance.

Funding Agency : DST

RTL to GSDII flow and DFT implementation

Funding Agency : Cypress Semiconductor Ltd. Bangalore

Unsigned binary division circuit using non-restoring division method

Funding Agency : Intel

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Patents

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Vidwan-ID : 228428

Academic

Score criteria

Vidwan Score 8.4

Prof Abhijit Rameshwar Asati

Publications

Journal Articles

Book

Conference Proceedings

Projects

Awards

Citations / H-Index

Altmetrics

Google Scholar

Co-author Network

Publications - 85 Co-author - 63

Expertise

Electrical and Electronic Engineering

Personal Information

Prof Abhijit Rameshwar Asati

Experience

Professor

Qualification

Ph.D

Honours and Awards

Senior member IEEE

Biography Published

project completion award

Senior member IEEE

Biography Published

project completion award

Doctoral Theses Guided

Methodologies for Area, Speed, and Power Optimizations in High-Level Synthesis for Diverse Applications

Design Exploration of Low Power Arithmetic and SRAM Circuits using Subthreshold Design Technique

Iris Localization in Iris Recognition System: Algorithms and Hardware Implementation

Methodologies for Area, Speed, and Power Optimizations in High-Level Synthesis for Diverse Applications

Design Exploration of Low Power Arithmetic and SRAM Circuits using Subthreshold Design Technique

Iris Localization in Iris Recognition System: Algorithms and Hardware Implementation

Framework for Translation of C/C++ Applications on Reconfigurable Computing Systems

Membership In Committees

IEEE

IEEE

IETE

IEEE

IEEE

IETE

Institution of Engineers India

'Metrology Society of India

Research Projects

Convolutional neural networks and their Hardware Implementation for Improved Performance.

Funding Agency : DST

RTL to GSDII flow and DFT implementation

Funding Agency : Cypress Semiconductor Ltd. Bangalore

Unsigned binary division circuit using non-restoring division method

Funding Agency : Intel

Convolutional neural networks and their Hardware Implementation for Improved Performance.

Funding Agency : DST

RTL to GSDII flow and DFT implementation

Funding Agency : Cypress Semiconductor Ltd. Bangalore

Unsigned binary division circuit using non-restoring division method

Funding Agency : Intel

Patents

A method of high level synthesis in integrated circuit design using application specific bit widths

Prateek Sikka; Abhijit Asati; Chandra Shekhar

A method of high level synthesis in integrated circuit design using application specific bit widths

Prateek Sikka; Abhijit Asati; Chandra Shekhar

Publications (85)

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Conference
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