Virendra Singh
VIDWAN ID: 52236

Dr Virendra Singh

Male Doctor of Philosophy
Associate Professor | Department of Electrical Engineering
Indian Institute of Technology, Bombay
Maharashtra
Expertise: Electrical and Electronic Engineering
212 Publications
0 Projects
1121 Scopus Citations
868 CrossRef
Publications
212 Total
Articles
30
Chapters
1
Proceedings
181
Activity

No publication activity to display.

Scopus Scopus
1,121 Citations
15 h-index
CrossRef CrossRef
868 Citations
13 h-index
Google Scholar Google Scholar

Loading Scholar statistics...

Professional Recognition

No Data Found

There is currently nothing to display here.

Community & Membership

No Data Found

There is currently nothing to display here.

No Data Found

There is currently nothing to display here.

Personal Details

Doctor of Philosophy
2005
N/A
Associate Professor
— – Present
Indian Institute of Technology, Bombay | Department of Electrical Engineering
Engineering and Technology
Electrical and Electronic Engineering

Related Profiles

Scholarly Work

No Data Found

There is currently nothing to display here.

No Data Found

There is currently nothing to display here.

FPGA BASED INTERNET OF THINGS DEVICE

INDIAN INSTITUTE OF TECHNOLOGY BOMBAY
- Patent No. : IN201821007807A Filed : 01-03-2018
Published : 06-09-2019 Published

Scholarly Publications

Instruction-based delay fault self-testing of processor cores

Conference Paper
Year: 2004. Volume: 17 , Pages: 933-938 .

Software-based delay fault testing of processor cores

Conference Paper
Year: 2003. Volume: 2003-January , Pages: 68-71 .
Authors: Singh; Inoue; Saluja; Fujiwara

Delay fault testing of processor cores in functional mode

Journal Article
IEICE Transactions on Information and Systems. Year: 2005. Volume: E88-D , Issue: 3 , Pages: 610-617 .
Authors: V. SINGH

Instruction-based self-testing of delay faults in pipelined processors

Journal Article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Year: 2006. Volume: 14 , Issue: 11 , Pages: 1203-1214 .
Authors: Virendra Singh; Michiko Inoue; Kewal K. Saluja; Hideo Fujiwara

Testing superscalar processors in functional mode

Conference Paper
Year: 2005. Volume: 2005 , Pages: 747-748 .
Authors: V. Singh; M. Inoue; K.K. Saluja; H. Fujiwara

Instruction-Based delay fault self-testing of pipelined processor cores

Conference Paper
Year: 2005. Pages: 5686-5689 .
Authors: V. Singh; M. Inoue; K.K. Saluja; H. Fujiwara

Polynomial coefficient based dc testing of non-linear analog circuits

Conference Paper
Year: 2009. Pages: 69-74 .
Authors: Suraj Sindia; Virendra Singh; Vishwani D. Agrawal

DX-compactor: Distributed X-compaction for SoCs

Conference Paper
Year: 2009. Pages: 505-510 .
Authors: Reshma C. Jumani; Niraj Bharatkumar Jain; Virendra Singh; Kewal K. Saluja
Showing 1 to 8 of 212 publications