Baljit Kaur
VIDWAN ID: 97042

Dr Baljit Kaur

Female Doctor of Philosophy
Assistant Professor | Department of Electronics and Communication Engineering
National Institute of Technology Delhi
Haryana
Expertise: Electrical and Electronic Engineering
86 Publications
0 Projects
339 Scopus Citations
301 CrossRef
9 Years 1 Month Total Experience
Publications
86 Total
Articles
19
Books
1
Chapters
2
Proceedings
64
Activity

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Scopus Scopus
339 Citations
10 h-index
CrossRef CrossRef
301 Citations
9 h-index
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Personal Details

Doctor of Philosophy
2015
Jawaharlal Nehru University
Assistant Professor
Aug 2017 – Present
National Institute of Technology Delhi | Department of Electronics and Communication Engineering
Engineering and Technology
Electrical and Electronic Engineering

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Scholarly Work

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Scholarly Publications

TSV induced stress model and its application in delay estimation

Conference Paper
Year: 2018.
Authors: Raghav Chawla; Sarita Yadav; Arvind Sharma; Baljit Kaur; Rajendra Pratap; Bulusu Anand

Modified PPPE architecture for two-dimensional radon transform computation

Conference Paper
Year: 2011.
Authors: Baljit Kaur; Manoj Kumar Majumder

Novel VLSI architecture for two-dimensional radon transform computations

Conference Paper
Year: 2012. Pages: 570-575 .
Authors: Baljit Kaur; Manoj Kumar Majumder

Leakage power estimation for ISCAS C17 benchmark circuit

Conference Paper
Year: 2019. Pages: 108-112 .

Efficient nanoscale VLSI standard cell library characterization using a novel delay model

Conference Paper
Year: 2011. Pages: 458-463 .
Authors: Sandeep Miryala; Baljit Kaur; Bulusu Anand; Sanjeev Manhas

An accurate current source model for CMOS based combinational logic cell

Conference Paper
Year: 2012. Pages: 561-565 .
Authors: Baljit Kaur; Sandeep Vundavalli; S. K. Manhas; S. Dasgupta; Bulusu Anand

Efficient ECSM characterization considering voltage, temperature, and mechanical stress variability

Journal Article
IEEE Transactions on Circuits and Systems I: Regular Papers. Year: 2014. Volume: 61 , Issue: 12 , Pages: 3407-3415 .
Authors: Baljit Kaur; Naushad Alam; S. K. Manhas; Bulusu Anand

A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization

Journal Article
Year: 2016. Volume: 53 , Pages: 45-55 .
Authors: Baljit Kaur; Arvind Sharma; Naushad Alam; S.K. Manhas; Bulusu Anand
Showing 1 to 8 of 86 publications