Prof Naushad Alam
Professor
| Department of Electronics Engineering
Aligarh Muslim University, Aligarh
Uttar Pradesh
Expertise:
Electrical and Electronic Engineering
44
Publications
1
Projects
675
Scopus Citations
706
CrossRef
9 Years 11 Months Total Experience
Scopus
675
Citations
11
h-index
CrossRef
706
Citations
13
h-index
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IEEE
MemberIETE
FellowPersonal Details
Doctor of Philosophy
2013
Jawaharlal Nehru University
Master of Technology
2009
Assam University, Silchar
Bachelor of Technology
2003
Maulana Azad National Urdu University
Professor
Oct 2019 – Present
Aligarh Muslim University, Aligarh
| Department of Electronics Engineering
Associate Professor
Oct 2016 – Oct 2019
Aligarh Muslim University, Aligarh
| Department of Electronics Engineering
Engineering and Technology
Scholarly Work
Design of Tunnel FET Based SRAM for IoT Applications
CompletedDesign of Memory Circuits in CMOS and Beyond CMOS Technology
Device-Circuit Co-Design for Low Power Applications
Ultra-Low Power Analog Integrated Circuits in Technologies Beyond CMOS
A Device Architecture for P-I-N Forward Leakage Current Suppression in TFET
Aligarh Muslim University
-
Application No. :
202211020357
Filed :
04-04-2022
Published :
29-04-2022
Filed
Robust and Low Power Static Random Access Memory Cell (RLP-SRAM)
Sayeed Ahmad
Naushad Alam and Mohd Hasan
-
Patent No. :
416535
Filed :
30-11--0001
Published :
30-11--0001
Published
Scholarly Publications
An analytical delay model for mechanical stress induced systematic variability analysis in nanoscale circuit design
An analytical delay model for CMOS inverter-transmission gate structure
10.1109/ISVDAT.2014.6881038
Crossref: 3
The impact of process-induced mechanical stress on multi-fingered device performance
Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance
Impact of dummy poly on the process-induced mechanical stress enhanced circuit performance
Gate-pitch optimization for circuit design using strain-engineered multifinger gate structures
The impact of process-induced mechanical stress in narrow width devices and circuit design issues
The impact of process-induced mechanical stress on d-latch timing performance
Showing 1 to 8 of 44 publications