Ministry of Education
Jagadesh Kumar Mamidala
VIDWAN ID: 43033

Prof Jagadesh Kumar Mamidala

Male Doctor of Philosophy
Chairman
University Grant Commission (2022)
Delhi
Expertise: Electrical and Electronic Engineering
ORCID 0000-0001-6657-1277 Scopus 7403637440 ResearcherID I-4264-2012 Google Scholar zgxxvhQAAAAJ
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284 Publications
0 Projects
2421 Scopus Citations
7634 CrossRef
27 Years 1 Month Total Experience
Publications
284 Total
Articles
234
Books
2
Chapters
1
Proceedings
47
Activity

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Scopus Scopus
2,421 Citations
25 h-index
CrossRef CrossRef
7,634 Citations
44 h-index
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Personal Details

Doctor of Philosophy
Indian Maritime University
Chairman
Jan 2022 – —
University Grant Commission
Professor (HAG)
Jun 2019 – Dec 1995
Indian Institute of Technology, Delhi | Department of Electrical Engineering
Vice Chancellor
Feb 2016 – Apr 2022
Jawaharlal Nehru University
Professor
Dec 1995 – Jul 2019
Indian Institute of Technology, Delhi | Department of Electrical Engineering
Engineering and Technology
Electrical and Electronic Engineering

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Scholarly Work

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Scholarly Publications

Realising wide bandgap P-SiC-emitter lateral heterojunction bipolar transistors with low collector-emitter offset voltage and high current gain: a novel proposal using numerical simulation

Journal Article
IEE Proceedings - Circuits, Devices and Systems. Year: 2004. Volume: 151 , Issue: 5 , Pages: 399 .
Authors: Kumar, M. J.; Reddy, C. L.
DOI 10.1049/ip-cds:20040295 Crossref Crossref: 6

Surface accumulation layer transistor (SALTran): A new bipolar transistor for enhanced current gain and reduced hot-carrier degradation

Journal Article
IEEE Transactions on Device and Materials Reliability. Year: 2004. Volume: 4 , Issue: 3 , Pages: 509-515 .
Authors: Kumar, M.J.; Parihar, V.
DOI 10.1109/TDMR.2004.829074 Crossref Crossref: 22

Inverse modeling of delta doped pseudomorphic high electron mobility transistors

Conference Paper
Journal of Vacuum Science & Technology A. Year: 2004. Volume: 22 , Issue: 3 , Pages: 1036-1039 .
Authors: Meena Mishra; M. Jagadesh Kumar; Yashvir Singh; S. R. Shukla; H. P. Vyas; D. S. Rawal; A. Naik; H. S. Sharma; B. K. Sehgal; R. Gulati
DOI 10.1116/1.1722299 Crossref Crossref: 2 Scopus Scopus: 3

Evidence for suppressed short-channel effects in deep submicron dual-material gate (DMG) partially depleted SOI MOSFETs - A two-dimensional analytical approach

Journal Article
Microelectronic Engineering. Year: 2004. Volume: 75 , Issue: 4 , Pages: 367-374 .
Authors: Kumar, M.J.; Reddy, G.V.
DOI 10.1016/j.mee.2004.07.058 Crossref Crossref: 13

Exploring the novel characteristics of fully depleted dual-material gate (DMG) SOI MOSFET using two-dimensional numerical simulation studies

Conference Paper
Year: 2004.
Authors: Chaudhry, A.; Kumar, M.J.

Investigation of the novel attributes of a fully depleted dual-material gate SOI MOSFET

Journal Article
IEEE Transactions on Electron Devices. Year: 2004. Volume: 51 , Issue: 9 , Pages: 1463-1467 .
Authors: Chaudhry, A.; Kumar, M.J.
DOI 10.1109/TED.2004.833961 Crossref Crossref: 124

Analytical model for the threshold voltage of Dual Material Gate (DMG) partially depleted SOI MOSFET and evidence for reduced short-channel effects

Conference Paper
Year: 2004.
Authors: Kumar, M.J.; Reddy, G.V.

Controlling Short-Channel Effects in Deep-Submicron SOI MOSFETs for Improved Reliability: A Review

Journal Article
IEEE Transactions on Device and Materials Reliability. Year: 2004. Volume: 4 , Issue: 1 , Pages: 99-109 .
Authors: Chaudhry, A.; Kumar, M.J.
DOI 10.1109/TDMR.2004.824359 Crossref Crossref: 442
Showing 49 to 56 of 284 publications