Ministry of Education
Vivek Venkataraman
VIDWAN ID: 70333

Prof Vivek Venkataraman

Male
Assistant Professor | Department of Electrical Engineering
Indian Institute of Technology, Delhi
Delhi
Expertise: Electrical and Electronic Engineering
Scopus 24777664700
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102 Publications
0 Projects
2249 Scopus Citations
2040 CrossRef
9 Years 2 Months Total Experience
Publications
102 Total
Articles
47
Proceedings
55
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Scopus Scopus
2,249 Citations
20 h-index
CrossRef CrossRef
2,040 Citations
20 h-index
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Assistant Professor
Jul 2017 – Present
Indian Institute of Technology, Delhi | Department of Electrical Engineering
Engineering and Technology
Electrical and Electronic Engineering

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A DEVICE AND STRUCTURE FOR CONTROLLING PARASITIC FRINGE CAPACITANCE

INDIAN INSTITUTE OF TECHNOLOGY DELHI
IN
- Patent No. : IN200601693I1 Filed : 24-07-2006
Published : 15-02-2008 Published

Scholarly Publications

A new grounded lamination gate (GLG) for diminished fringe-capacitance effects in high-κ gate-dielectric MOSFETs

Journal Article
IEEE Transactions on Electron Devices. Year: 2006. Volume: 53 , Issue: 10 , Pages: 2578-2581 .
Authors: Kumar, M.J.; Venkataraman, V.; Gupta, S.K.
DOI 10.1109/TED.2006.882268 Crossref Crossref: 1 Scopus Scopus: 1

A simple analytical threshold voltage model of nanoscale single-layer fully depleted strained-silicon-on-insulator MOSFETs

Journal Article
IEEE Transactions on Electron Devices. Year: 2006. Volume: 53 , Issue: 10 , Pages: 2500-2506 .
Authors: Kumar, M.J.; Venkataraman, V.; Nawal, S.
DOI 10.1109/TED.2006.882041 Crossref Crossref: 42 Scopus Scopus: 48

Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs

Journal Article
IEEE Transactions on Electron Devices. Year: 2006. Volume: 53 , Issue: 4 , Pages: 706-711 .
Authors: Kumar, M.J.; Gupta, S.K.; Venkataraman, V.
DOI 10.1109/TED.2006.870424 Crossref Crossref: 38 Scopus Scopus: 44

Compact modeling of threshold voltage in nanoscale strained-Si/SiGe MOSFETs

Conference Paper
Year: 2006.
Authors: Nawal, S.; Venkataraman, V.; Kumar, M.J.

On the parasitic gate capacitance of small-geometry MOSFETs

Journal Article
IEEE Transactions on Electron Devices. Year: 2005. Volume: 52 , Issue: 7 , Pages: 1676-1677 .
Authors: Kumar, M.J.; Venkataraman, V.; Gupta, S.K.
DOI 10.1109/TED.2005.850630 Crossref Crossref: 5 Scopus Scopus: 7

Analytical drain current model of nanoscale strained-Si/SiGe MOSFETs for analog circuit simulation

Conference Paper
Year: 2007. Pages: 189-194 .
Authors: Kumar, M.J.; Venkataraman, V.; Nawal, S.
DOI 10.1109/VLSID.2007.38 Crossref Crossref: 5 Scopus Scopus: 9

Compact analytical threshold-voltage model of nanoscale fully depleted etrained-silicon on silicon-germanium-on-insulator (SGOI) MOSFETs

Journal Article
IEEE Transactions on Electron Devices. Year: 2007. Volume: 54 , Issue: 3 , Pages: 554-562 .
Authors: Venkataraman, V.; Nawal, S.; Kumar, M.J.
DOI 10.1109/TED.2006.890369 Crossref Crossref: 54 Scopus Scopus: 63

Comprehensive approach to modeling threshold voltage of nanoscale strained silicon SOI MOSFETs

Journal Article
Journal of Computational Electronics. Year: 2007. Volume: 6 , Issue: 4 , Pages: 439-444 .
Authors: Kumar, M.J.; Venkataraman, V.; Nawal, S.
DOI 10.1007/s10825-007-0153-7 Crossref Crossref: 16 Scopus Scopus: 18
Showing 1 to 8 of 102 publications