Amit Saxena
VIDWAN ID: 555034

Dr Amit Saxena

Male Doctor of Philosophy
Associate Professor | Department of Electronics and Communication Engineering
Maharaja Agrasen Institute of Technology
Delhi
Expertise: Electrical and Electronic Engineering
12 Publications
0 Projects
48 Scopus Citations
38 CrossRef
21 Years 2 Months Total Experience
Publications
12 Total
Articles
7
Proceedings
5
Activity

No publication activity to display.

Scopus Scopus
48 Citations
5 h-index
CrossRef CrossRef
38 Citations
4 h-index
Google Scholar Google Scholar

Loading Scholar statistics...

Professional Recognition

No Data Found

There is currently nothing to display here.

Community & Membership

No Data Found

There is currently nothing to display here.

No Data Found

There is currently nothing to display here.

Personal Details

Doctor of Philosophy
2023
N/A
Associate Professor
Jul 2005 – Present
Maharaja Agrasen Institute of Technology | Department of Electronics and Communication Engineering
Engineering and Technology
Electrical and Electronic Engineering

Related Profiles

Scholarly Work

No Data Found

There is currently nothing to display here.

No Data Found

There is currently nothing to display here.

No Data Found

There is currently nothing to display here.

Scholarly Publications

Small signal model parameter extraction for cylindrical silicon-on-insulator Schottky barrier MOSFET

Journal Article
Microsystem Technologies. Year: 2023. Volume: 29 , Issue: 4 , Pages: 645-654 .
Authors: Saxena, A.; Kumar, M.; Sharma, R.K.; Gupta, R.S.

SOI Schottky Barrier Nanowire MOSFET with Reduced Ambipolarity and Enhanced Electrostatic Integrity

Journal Article
Journal of Electronic Materials. Year: 2020. Volume: 49 , Issue: 7 , Pages: 4450-4456 .
Authors: Amit Saxena; Manoj Kumar; R. K. Sharma; R. S. Gupta

Analytical modeling of cylindrical Silicon-on-Insulator Schottky Barrier MOSFET and impact of insulator pillar radius on analog/RF and linearity parameters for low power circuit application

Journal Article
Microelectronics Journal. Year: 2025. Volume: 156 , Pages: 106505 .
Authors: Jitender Kumar; Amit Saxena; S.S. Deswal; Aparna N. Mahajan; R.S. Gupta

RF and linearity parameters analysis of 20 nm gate-all-around gate-stacked junction-less accumulation mode MOSFET for low power circuit applications

Journal Article
Microsystem Technologies. Year: 2024. Volume: 30 , Issue: 6 , Pages: 673-685 .
Authors: Jitender Kumar; Aparna N. Mahajan; S. S. Deswal; Amit Saxena; R. S. Gupta

Extraction of non-quasi-static model parameters for cylindrical gate-stacked junction-less accumulation mode MOSFET and its implementation as RF filters for circuit applications

Journal Article
Microsystem Technologies. Year: 2023. Volume: 29 , Issue: 10 , Pages: 1431-1442 .
Authors: Jitender Kumar; Aparna N. Mahajan; S. S. Deswal; Amit Saxena; R. S. Gupta

Design of Low Power Analog/RF Signal Processing Circuits Using 22 nm Silicon-on-Insulator Schottky Barrier Nano-Wire MOSFET

Journal Article
International Journal of High Speed Electronics and Systems. Year: 2024. Volume: 33 , Issue: 01 , Pages: 2450003 .
Authors: Kumar, J.; Mahajan, A.N.; Deswal, S.S.; Saxena, A.; Gupta, R.S.

Implementation of High-K Gate Dielectric in Cylindrical SOI Schottky Barrier MOSFET for Enhanced I<sub>ON</sub>/I<sub>OFF</sub> Ratio

Conference Paper
Year: 2024. Pages: 1-4 .
Authors: Uppal, N.; Saxena, A.; Nath, V.; Gupta, R.S.

Gate All Around 22 nm SOI Schottky Barrier MOSFET with High I<sub>ON</sub>/I<sub>OFF</sub> Current Ratio for Low-Power Digital and Analog Circuit Applications

Conference Paper
Year: 2023. Pages: 65-72 .
Authors: Saxena, A.; Sharma, R.K.; Kumar, M.; Gupta, R.S.
Showing 1 to 8 of 12 publications