Ministry of Education
Archana Pandey
VIDWAN ID: 532242

Dr Archana Pandey

Female Doctor of Philosophy
Assistant Professor | Department of Electronics and Communication Engineering
Jaypee Institute of Information Technology, Noida
Uttar Pradesh
Expertise: Electrical and Electronic Engineering
ORCID 0000-0003-1927-1196 Scopus 55618021000
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25 Publications
0 Projects
63 Scopus Citations
143 CrossRef
9 Years 2 Months Total Experience
Publications
25 Total
Articles
16
Books
1
Chapters
1
Proceedings
7
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Scopus Scopus
63 Citations
4 h-index
CrossRef CrossRef
143 Citations
6 h-index
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Personal Details

Doctor of Philosophy
2017
N/A
Assistant Professor
Jul 2017 – Present
Jaypee Institute of Information Technology, Noida | Department of Electronics and Communication Engineering
Engineering and Technology
Electrical and Electronic Engineering

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Scholarly Publications

Effect of load capacitance and input transition time on FinFET inverter capacitances

Journal Article
IEEE Transactions on Electron Devices. Year: 2014. Volume: 61 , Issue: 1 , Pages: 30-36 .
Authors: Archana Pandey; Swati Raycha; Satish Maheshwaram; Sanjeev K. Manhas; Sudeb Dasgupta; Ashok K. Saxena; Bulusu Anand
DOI 10.1109/TED.2013.2291013 Crossref Crossref: 33 Scopus Scopus: 35

FinFET device capacitances: Impact of input transition time and output load

Conference Paper
Year: 2013. Pages: 371-373 .
Authors: Archana Pandey; Swati Raycha; S. Maheshwaram; S. K. Manhas; S. Dasgupta; A. K. Saxena; Bulusu Anand
DOI 10.1109/INEC.2013.6466050 Crossref Crossref: 4 Scopus Scopus: 3

Improved Underlap FinFET with Asymmetric Spacer Permittivities

Conference Paper
Year: 2014. Pages: 267-268 .
Authors: Saurabh K. Nema; M. SaiKiran; P. Singh; Archana Pandey; S. K. Manhas; A. K. Saxena; Anand Bulusu
DOI 10.1007/978-3-319-03002-9_67

FinFET Device Circuit Co-design Issues: Impact of Circuit Parameters on Delay

Conference Paper
Year: 2016. Volume: 2016-March , Pages: 288-293 .
Authors: Archana Pandey; Harsh Kumar; Praanshu Goyal; Sudeb Dasgupta; Sanjeev Kumar Manhas; Anand Bulusu
DOI 10.1109/VLSID.2016.15 Crossref Crossref: 1 Scopus Scopus: 2

A Modified Method of Logical Effort for FinFET Circuits Considering Impact of Fin-Extension Effects

Journal Article
Year: 2018.
Authors: Pandey, Archana; Garg, Pitul; Tyagi, Shobhit; Ranjan, Rajeev; Bulusu, Anand

Comparative Design and Analysis of FinFET and CMOS SRAM Cell

Conference Paper
Year: 2019. Pages: 275-278 .
Authors: Sharma, Y.; Singh, A.; Pandey, A.
DOI 10.1109/ICSC45622.2019.8938343 Crossref Crossref: 4

A Novel 20nm FinFET Based 10T SRAM Cell Design for Improved Performance

Book
Year: 2019. Pages: 523-531 .
Authors: Singh, A.; Sharma, Y.; Sharma, A.; Pandey, A.
DOI 10.1007/978-981-32-9767-8_43 Crossref Crossref: 5

Performance Evaluation of Stacked Gate Oxide/High K Spacers Based Gate All Around Device Architectures at 10 nm Technology Node

Journal Article
SILICON. Year: 2022. Volume: 14 , Issue: 5 , Pages: 2397-2407 .
Authors: Narula, M.S.; Pandey, A.
DOI 10.1007/s12633-022-01685-9 Crossref Crossref: 19
Showing 1 to 8 of 25 publications