Ministry of Education
Narendar V
VIDWAN ID: 154172

Dr Narendar V

Male
Assistant Professor (Grade-I) | Department of Electronics and Communication Engineering
National Institute of Technology, Warangal
Expertise: Electrical and Electronic Engineering
Scopus 56342552600
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75 Publications
0 Projects
1415 Scopus Citations
1279 CrossRef
8 Years 5 Months Total Experience
Publications
75 Total
Articles
64
Proceedings
11
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Scopus Scopus
1,415 Citations
23 h-index
CrossRef CrossRef
1,279 Citations
22 h-index
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Assistant Professor (Grade-I)
Apr 2018 – Present
National Institute of Technology, Warangal | Department of Electronics and Communication Engineering
Engineering and Technology
Electrical and Electronic Engineering

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Scholarly Work

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Scholarly Publications

Suppression of short channel effects (SCEs) by dual material gate vertical surrounding gate (DMGVSG) MOSFET: 3-D TCAD simulation

Open Access
Conference Paper
Procedia Engineering. Year: 2013. Volume: 64 , Pages: 125-132 .
Authors: Bhanu Chandar, D.; Vadthiya, N.; Kumar, A.; Mishra, R.A.
DOI 10.1016/j.proeng.2013.09.083 Crossref Crossref: 10 Scopus Scopus: 14

A two-dimensional (2D) analytical surface potential and subthreshold current model for the underlap dual-material double-gate (DMDG) FinFET

Journal Article
Journal of Computational Electronics. Year: 2016. Volume: 15 , Issue: 4 , Pages: 1316-1325 .
Authors: Vadthiya Narendar; Saurabh Rai; Siddharth Tiwari
DOI 10.1007/s10825-016-0899-x Crossref Crossref: 24 Scopus Scopus: 26

Junctionless Gate-all-around Nanowire FET with Asymmetric Spacer for Continued Scaling

Journal Article
SILICON. Year: 2022. Volume: 14 , Issue: 13 , Pages: 7461-7471 .
Authors: V. Bharath Sreenivasulu; Vadthiya Narendar
DOI 10.1007/s12633-021-01471-z Crossref Crossref: 33 Scopus Scopus: 28

On the design of p-channel step-FinFET at sub-10nm node: A parametric analysis

Journal Article
Year: 2022. Volume: 126 .
Authors: Santosh Kumar Padhi; Vadthiya Narendar; Atul Kumar Nishad
DOI 10.1016/j.mejo.2022.105505 Crossref Crossref: 8 Scopus Scopus: 9

Design and Temperature Assessment of Junctionless Nanosheet FET for Nanoscale Applications

Journal Article
SILICON. Year: 2022. Volume: 14 , Issue: 8 , Pages: 3823-3834 .
Authors: V. Bharath Sreenivasulu; Vadthiya Narendar
DOI 10.1007/s12633-021-01145-w Crossref Crossref: 69 Scopus Scopus: 79

A Comprehensive Analysis of Junctionless Tri-Gate (TG) FinFET Towards Low-Power and High-Frequency Applications at 5-nm Gate Length

Journal Article
SILICON. Year: 2022. Volume: 14 , Issue: 5 , Pages: 2009-2021 .
Authors: V. Bharath Sreenivasulu; Vadthiya Narendar
DOI 10.1007/s12633-021-00987-8 Crossref Crossref: 50 Scopus Scopus: 45

Junctionless SOI FinFET with advanced spacer techniques for sub-3 nm technology nodes

Journal Article
AEU - International Journal of Electronics and Communications. Year: 2022. Volume: 145 .
Authors: V. Bharath Sreenivasulu; Vadthiya Narendar
DOI 10.1016/j.aeue.2021.154069 Crossref Crossref: 41 Scopus Scopus: 47

P-Type Trigate Junctionless Nanosheet MOSFET: Analog/RF, Linearity, and Circuit Analysis

Journal Article
ECS Journal of Solid State Science and Technology. Year: 2021. Volume: 10 , Issue: 12 .
Authors: Bharath Sreenivasulu Vakkalakula; Narendar Vadthiya
DOI 10.1149/2162-8777/ac3bdf Crossref Crossref: 24 Scopus Scopus: 29
Showing 1 to 8 of 75 publications