Rahul Shrestha
VIDWAN ID: 113371

Dr Rahul Shrestha

Male Doctor of Philosophy
Associate Professor | School of Computing and Electrical Engineering
Indian Institute of Technology, Mandi
Himachal Pradesh
Expertise: Electrical and Electronic Engineering
72 Publications
0 Projects
706 Scopus Citations
629 CrossRef
9 Years 9 Months Total Experience
Publications
72 Total
Articles
32
Proceedings
40
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Scopus Scopus
706 Citations
13 h-index
CrossRef CrossRef
629 Citations
13 h-index
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Personal Details

Doctor of Philosophy
2014
Indian Institute of Technology, Kharagpur
Associate Professor
Dec 2016 – Present
Indian Institute of Technology, Mandi | School of Computing and Electrical Engineering
Engineering and Technology
Electrical and Electronic Engineering

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Scholarly Publications

Hardware implementation of Max-Log-MAP algorithm based on MacLaurin series for turbo decoder

Conference Paper
Year: 2011. Pages: 509-511 .
Authors: Rahul Shrestha; Roy Paily

A novel architecture for computing eigenvalues of matrix for high speed applications

Conference Paper
Year: 2017.
Authors: Soumitr Sanjay Dubey; Rahul Shrestha; Shubhajit Roy Chowdhury

VLSI-design and FPGA-implementation of GMSK-demodulator architecture using CORDIC engine for low-power application

Conference Paper
Year: 2017.
Authors: Lalit Kumar; Deepak Kumar Mittal; Rahul Shrestha

Design of low power VLSI-architecture and ASIC implementation of fuzzy logic based automatic car-parking system

Conference Paper
Year: 2017.
Authors: Enna Sachdeva; Pratik Porwal; Nalini Vidyulatha; Rahul Shrestha

Energy-efficient VLSI architecture & Implementation of Bi-modal multi-banked register-file organization

Conference Paper
Year: 2017. Volume: 711 , Pages: 299-312 .
Authors: Sumanth Gudaparthi; Rahul Shrestha

A new multi-objective hardware-software-partitioning algorithmic approach for high speed applications

Conference Paper
Year: 2017. Volume: 711 , Pages: 62-68 .
Authors: Naman Govil; Rahul Shrestha; Shubhajit Roy Chowdhury

VLSI architecture for cyclostationary feature detection based spectrum sensing for cognitive-radio wireless networks and its ASIC implementation

Conference Paper
Year: 2016. Volume: 2016-September , Pages: 69-74 .
Authors: Mahesh S. Murty; Rahul Shrestha

Memory-Reduced Maximum A Posteriori Probability Decoding for High-Throughput Parallel Turbo Decoders

Journal Article
Circuits, Systems, and Signal Processing. Year: 2016. Volume: 35 , Issue: 8 , Pages: 2832-2854 .
Authors: Rahul Shrestha; Roy Paily
Showing 1 to 8 of 72 publications