Rahul Shrestha
VIDWAN ID: 113371

Dr Rahul Shrestha

Male Doctor of Philosophy
Associate Professor | School of Computing and Electrical Engineering
Indian Institute of Technology, Mandi
Himachal Pradesh
Expertise: Electrical and Electronic Engineering
72 Publications
0 Projects
706 Scopus Citations
629 CrossRef
9 Years 9 Months Total Experience
Publications
72 Total
Articles
32
Proceedings
40
Activity

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Scopus Scopus
706 Citations
13 h-index
CrossRef CrossRef
629 Citations
13 h-index
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Personal Details

Doctor of Philosophy
2014
Indian Institute of Technology, Kharagpur
Associate Professor
Dec 2016 – Present
Indian Institute of Technology, Mandi | School of Computing and Electrical Engineering
Engineering and Technology
Electrical and Electronic Engineering

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Scholarly Work

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Scholarly Publications

Low-Latency and Reconfigurable VLSI-Architectures for Computing Eigenvalues and Eigenvectors Using CORDIC-Based Parallel Jacobi Method

Journal Article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Year: 2022. Volume: 30 , Issue: 8 , Pages: 1020-1033 .
Authors: Sharma, R.; Shrestha, R.; Sharma, S.K.

VLSI Architectures and Hardware Implementation of Ultra Low-Latency and Area-Efficient Pietra-Ricci Index Detector for Spectrum Sensing

Journal Article
IEEE Transactions on Circuits and Systems I: Regular Papers. Year: 2024. Volume: 71 , Issue: 5 , Pages: 2348-2361 .
Authors: Elivander Judas Tadeu Pereira; Dayan Adionel Guimarães; Rahul Shrestha

Energy-Efficient and High-Throughput CNN Inference Engine Based on Memory-Sharing and Data-Reusing for Edge Applications

Journal Article
IEEE Transactions on Circuits and Systems I: Regular Papers. Year: 2024. Volume: 71 , Issue: 7 , Pages: 3189-3202 .
Authors: Md. Najrul Islam; Rahul Shrestha; Shubhajit Roy Chowdhury

Energy-Preserving Indirect-Feedback for Wireless Power Transfer: Algorithm and Hardware Architecture

Journal Article
IEEE Transactions on Green Communications and Networking. Year: 2025. Volume: 9 , Issue: 4 , Pages: 1851-1865 .
Authors: Siddhartha Sarma; Rahul Shrestha; Rohit B. Chaurasiya

CRIS-b: A High-Speed Unified Modulo Reduction Algorithm and Hardware Architecture for CRYSTALS-Kyber

Conference Paper
Year: 2025. Pages: 49-54 .
Authors: Alip Majumdar; Rahul Shrestha

Reconfigurable and Hardware-Efficient KECCAK Architecture with SHAKE Integration and Dynamic Input Processing for Post Quantum Cryptography

Conference Paper
Year: 2025.

Hardware-Efficient Architectures and Low-Complexity Algorithms for Multi-Coset Sub-Nyquist Sampling-Based Wideband Spectrum Sensor for Dynamic Spectrum Access

Journal Article
Authors: Aayush Shrivas; Rahul Shrestha; Dron Sankhala; Rohit B. Chaurasiya

Design and FPGA Implementation of Power and Area Efficient Multi-Stage Accelerator for Depthwise Separable Convolutions

Conference Paper
Year: 2026. Pages: 19-24 .
Authors: Srishti Misra; Rahul Shrestha
Showing 49 to 56 of 72 publications