Rishu Chaujar
VIDWAN ID: 67067

Prof Rishu Chaujar

Female Doctor of Philosophy
Professor
Delhi Technological University
Delhi
Expertise: Electrical and Electronic Engineering
171 Publications
0 Projects
1680 Scopus Citations
2604 CrossRef
16 Years 2 Months Total Experience
Publications
171 Total
Articles
81
Books
2
Chapters
3
Proceedings
85
Activity

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Scopus Scopus
1,680 Citations
24 h-index
CrossRef CrossRef
2,604 Citations
31 h-index
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Professional Recognition

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Personal Details

Doctor of Philosophy
N/A
Professor
Aug 2021 – Present
Delhi Technological University
Associate Professor
Aug 2018 – Aug 2021
Delhi Technological University
Assistant Professor
Jul 2010 – Jul 2018
Delhi Technological University | Department of Applied Physics
Engineering and Technology
Electrical and Electronic Engineering

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Scholarly Work

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Scholarly Publications

On-state and RF performance investigation of sub-50 nm L-DUMGAC MOSFET design for high-speed logic and switching applications

Journal Article
Semiconductor Science & Technology. Year: 2008. Volume: 23 , Issue: 9 , Pages: 095009 .
Authors: Chaujar, R.; Kaur, R.; Saxena, M.; Gupta, M.; Gupta, R.S.

Pre-distortion assessment of workfunction engineered multilayer dielectric design of DMGISE SON MOSFET

Conference Paper
Year: 2008.
Authors: Kaur, R.; Chaujar, R.; Saxena, M.; Gupta, R.S.

Solution to CMOS technology for high performance analog applications: GEWE-RC MOSFET

Conference Paper
Year: 2008.
Authors: Chaujar, R.; Kaur, R.; Saxena, M.; Gupta, M.; Gupta, R.S.

TCAD assessment of gate electrode workfunction engineered recessed channel (GEWE-RC) MOSFET and its multilayered gate architecture - Part I: Hot-carrier-reliability evaluation

Journal Article
IEEE Transactions on Electron Devices. Year: 2008. Volume: 55 , Issue: 10 , Pages: 2602-2613 .
Authors: Chaujar, R.; Kaur, R.; Saxena, M.; Gupta, M.; Gupta, R.S.

TCAD performance investigation of a novel MOSFET architecture of Dual Material Gate Insulated Shallow Extension Silicon On Nothing (DMG ISE SON) MOSFET for ULSI era

Conference Paper
Year: 2008. Pages: 1-4 .
Authors: Kaur, R.; Chaujar, R.; Saxena, M.; Gupta, R.S.

Two-dimensional analytical sub-threshold model of multi-layered gate dielectric recessed channel (MLaG-RC) nanoscale MOSFET

Journal Article
Semiconductor Science & Technology. Year: 2008. Volume: 23 , Issue: 4 , Pages: 045006 .
Authors: Chaujar, R.; Kaur, R.; Saxena, M.; Gupta, M.; Gupta, R.S.

Hot-carrier reliability and analog performance investigation of DMG-ISEGaS MOSFET

Journal Article
IEEE Transactions on Electron Devices. Year: 2007. Volume: 54 , Issue: 9 , Pages: 2556-2561 .
Authors: Kaur, R.; Chaujar, R.; Saxena, M.; Gupta, R.S.

Lateral channel engineered hetero material insulated shallow extension gate stack (HMISEGAS) MOSFET structure: High performance RF solution for MOS technology

Journal Article
Semiconductor Science & Technology. Year: 2007. Volume: 22 , Issue: 10 , Pages: 1097-1103 .
Authors: Kaur, R.; Chaujar, R.; Saxena, M.; Gupta, R.S.
Showing 1 to 8 of 171 publications