Dr Abhishek Acharya
Associate Professor
| Department of Electronics Engineering
Sardar Vallabhbhai National Institute of Technology, Surat
Gujarat
Expertise:
Electrical and Electronic Engineering
74
Publications
8
Projects
263
Scopus Citations
237
CrossRef
23 Years 1 Month Total Experience
Scopus
263
Citations
10
h-index
CrossRef
237
Citations
10
h-index
Google Scholar
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Professional Recognition
Google Gift Funding of USD 30000
2024
Google Inc. Singapore
International Travel Grant
2017
IIT Roorkee
Senior IEEE Member
2021
IEEE Society, USA
Community & Membership
IEEE Computer Society Technical Community on VLSI
MemberIEEE SIGHT
MemberIEEE
Senior MemberIEEE Nanotechnology Council
MemberIEEE Young Professionals
MemberIEEE Circuits and Systems Society Membership
MemberIEEE Electron Devices Society Membership
MemberIEEE Solid-State Circuits Society Membership
MemberPersonal Details
Doctor of Philosophy
2019
Jawaharlal Nehru University
Associate Professor
Dec 2023 – Present
Sardar Vallabhbhai National Institute of Technology, Surat
| Department of Electronics Engineering
Assistant Professor
Dec 2019 – Dec 2023
Sardar Vallabhbhai National Institute of Technology, Surat
| Department of Electronics Engineering
Assistant Professor
Aug 2003 – Nov 2019
Engineering College,Bikaner
Engineering and Technology
Scholarly Work
Development of IoT Edge Computing Applications using Optimized Near Threshold Voltage (NTV) Standard Cells with OPENLANE
OtherDesign and Characterization of Radiation Hardened Standard Cell Library using Nanosheet Field Effect Transistors: Improving on Design Margins/Reliability
OtherSecure and Energy efficient Mixed domain Compute in memory-based AI accelerator Chip for Edge applications
OtherDesign, Fabrication and Characterization of optimized 2D-Material SOT-MTJ for Energy Efficient Embedded Memory (MRAM) / Sensing Applications
OtherDesign and Fabrication of BiOI-based Indoor Photovoltaic Devices for Development of Self-Powered IoT Ecosystem
OtherDevelopment of Speech based Mobile Application for Lung Disease Detection
OtherA TCAD Framework for Assessment of Spacer Material and Back-Gate Bias on the Electrical Performance of Negative Capacitance FETs
CompletedInvestigation of Hybrid TFET/FinFET based Circuit Design Methodology for the Ultra Low Power Applications
CompletedDesign and Optimization of Gate-All-Around Nanosheet Field-effect Transistor: A Physical Insight
Advancing Spin-Orbit Torque Magnetic Tunnel Junctions for Scalable Field-Free Switching and Logic-in-Memory Architectures
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Scholarly Publications
Efficient total ionizing dose-aware standard cell characterization methodology for path-level timing performance in nanoscale digital circuit applications
Unveiling the Impact of Non-Ideal Gate in Stacked Nanosheet FETs
Epitaxial Layer-Based Si/SiGe Hetero-Junction Line Tunnel FETs: A Physical Insight
Open AccessPerformance optimization of III–V homo/heterojunction line TFET: Device-circuit Interaction
Performance Assessment of Spacer Engineered Si/SiGe Line Tunnel FETs
Impact of Body Bias on Metal–Ferroelectric–Insulator Stacked Si/SiGe Negative Capacitance Line TFET: A Physical Insight
Self-Heating Aware Performance Investigation of Vertically and Sideway Stacked GAA Nanowire FETs at Sub-5nm Technology Node
Self-SHE Pulse-Enabled 2-D Material-Based SOT-MTJ: A Scalable and Energy-Efficient Write Circuit for LiM Architectures
10.1109/TCAD.2025.3596763
Crossref: 1
Showing 1 to 8 of 74 publications