Anjaneyulu P
VIDWAN ID: 247681

Mr Anjaneyulu P

Male Master of Technology
Assistant Professor | Department of Electronics and Communication Engineering
MLR Institute of Technology, Hyderabad
Telangana
Expertise: Electrical and Electronic Engineering
18 Publications
0 Projects
165 Scopus Citations
68 CrossRef
12 Years 3 Months Total Experience
Publications
18 Total
Articles
10
Proceedings
8
Activity

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Scopus Scopus
165 Citations
7 h-index
CrossRef CrossRef
68 Citations
4 h-index
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ISTE
Life Member
Jan 2015

Personal Details

Master of Technology
2014
N/A
Assistant Professor
Jun 2014 – Present
MLR Institute of Technology, Hyderabad | Department of Electronics and Communication Engineering
Engineering and Technology
Electrical and Electronic Engineering

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Scholarly Work

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Scholarly Publications

Content-based image retrieval using genetic algorithm retrieval effectiveness in terms of precision and recall

Journal Article
Authors: Gantala, A.; Telagam, N.; Kumar, G.V.; Anjaneyulu, P.; Murali Prasad, R.

An elegant method for delay estimation in mobile applications

Journal Article
Authors: Shaik, S.B.; Gantala, A.; Anjaneyulu, P.

Design of circular microstrip patch antenna and its simulation results

Journal Article
Authors: Gade, M.S.L.; Nagendra Prasad, G.; Gantala, A.; Anjaneyulu, P.; Hasane Ahammad, S.

Implementation of digital beam former for phased array radar

Conference Paper
Year: 2017. Pages: 242-244 .
Authors: Anjaneyulu, P.; Pallavi, N.; Reddy, P.B.; Mahendra, V.; Karthik, R.

Design and interfacing of T/R modules with radar system through TR module controller using FPGA

Conference Paper
Year: 2017. Pages: 231-233 .
Authors: Pallavi, N.; Anjaneyulu, P.; Natarajan, P.B.; Mahendra, V.; Karthik, R.

Design and implementation of linear frequency modulated waveform using DDS and FPGA

Conference Paper
Year: 2017. Pages: 237-241 .
Authors: Pallavi, N.; Anjaneyulu, P.; Reddy, P.B.; Mahendra, V.; Karthik, R.

Air writing recognition modeling and recognition of characters, words and connecting motions

Conference Paper
Year: 2018. Pages: 1112-1115 .
Authors: Anjaneyulu, P.; Jampaiah, Y.; Karthik, R.; Vijetha, T.

9-bit parity generator using XO4 and XO7 technology

Journal Article
Authors: Sravana, J.; Ajitha, G.; Srihari, C.; Ranjitha, S.; Anjaneyulu, P.
Showing 9 to 16 of 18 publications