Jujavarapu Sravana
VIDWAN ID: 217092

Mrs Jujavarapu Sravana

Female Doctor of Philosophy
Assistant Professor
Malla Reddy Engineering College for women
Telangana
Expertise: Electrical and Electronic Engineering
13 Publications
0 Projects
162 Scopus Citations
60 CrossRef
13 Years 3 Months Total Experience
Publications
13 Total
Articles
4
Chapters
3
Proceedings
6
Activity

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Scopus Scopus
162 Citations
6 h-index
CrossRef CrossRef
60 Citations
4 h-index
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Professional Recognition

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Community & Membership

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IETE
Life time
Jan 2015

Personal Details

Doctor of Philosophy
2022
University of Delhi
Master of Technology
2011
N/A
Assistant Professor
Sep 2024 – Present
Malla Reddy Engineering College for women
Assistant Professor
Mar 2022 – Sep 2024
Geethanjali College of Engineering and Technology | Electronics and Communication Engineering
Assistant Professor
Jun 2013 – Mar 2022
Institute of Aeronautical Engineering | Electronics and Communication Engineering
Engineering and Technology
Electrical and Electronic Engineering

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Scholarly Work

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Scholarly Publications

Analysis of optical, structural, thermodynamics and electronic properties of silicon tetrafluoride using first-principles analysis under different hydrostatic pressure and composition

Journal Article
Physica Scripta. Year: 2025. Volume: 100 , Issue: 6 .
Authors: Sravana J; P Muralidhar; Vundela Padmanabha Reddy

Realısatıon of Performance Optımısed 32-Bıt Vedıc Multıplıer

Open Access
Journal Article
Year: 2022. Volume: 4 , Issue: 2 , Pages: 14-21 .

Novel Methodology to Validate DUTs Using Single Access Structure

Conference Paper
Year: 2021.
Authors: Chandra Shaker Pittala; J. Sravana; G. Ajitha; P. Saritha; Mohammad Khadir; V. Vijay; S. China Venkateswarlu; Rajeev Ratna Vallabhuni

Novel Architecture for Logic Test Using Single Cycle Access Structure

Open Access
Journal Article
Year: 2021. Volume: 3 , Issue: 1 , Pages: 1-6 .

A Comparative Analysis and Ideas to Reduce Various Leakage Power in Modern VLSI

Book Chapter
Year: 2023. Pages: 177-191 .
Authors: Sravana, J.; Karthik, A.; Dinesh, T.

9-bit parity generator using XO4 and XO7 technology

Journal Article
Authors: Sravana, J.; Ajitha, G.; Srihari, C.; Ranjitha, S.; Anjaneyulu, P.

Implementation of Spurious Power Suppression based Radix-4 Booth Multiplier using Parallel Prefix Adders

Conference Paper
Year: 2022. Pages: 428-433 .
Authors: Sravana, J.; Hima Bindhu, S.K.; Sharvani, K.; Sai Preethi, P.; Sanyal, S.; Vijay, V.V.V.; Vallabhuni, R.R.

Optimized VLSI Design of Squaring Multiplier Using Yavadunam Sutra Through Deficiency Bits Reduction

Book Chapter
Year: 2022. Pages: 387-399 .
Authors: J. Sravana; K. S. Indrani; Sankeerth Mahurkar; M. Pranathi; D. Rakesh Reddy; Vijay Vallabhuni
Showing 1 to 8 of 13 publications