S. Gurunarayanan
VIDWAN ID: 228397

Prof S. Gurunarayanan

Male Doctor of Philosophy
Senior Professor | Department of Electrical and Electronics engineering
Birla Institute of Technology & Sciences, Pilani
Telangana
Expertise: Electrical and Electronic Engineering
65 Publications
0 Projects
311 Scopus Citations
245 CrossRef
39 Years Total Experience
Publications
65 Total
Articles
22
Proceedings
43
Activity

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Scopus Scopus
311 Citations
9 h-index
CrossRef CrossRef
245 Citations
8 h-index
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Professional Recognition

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Personal Details

Doctor of Philosophy
2000
Central Institute of Post Harvest Engineering and Technology
Senior Professor
Sep 1987 – Present
Birla Institute of Technology & Sciences, Pilani | Department of Electrical and Electronics engineering
Engineering and Technology
Electrical and Electronic Engineering

Related Profiles

Scholarly Work

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Techniques to improve the performance of cache memory for multi core processors

University Birla Institute of Technology and Science Pilani
Year 2015
Downloads 0

Energy efficient techniques for multi-tasking embedded systems - cache design and task scheduling algorithms

University Birla Institute of Technology and Science Pilani
Year 2009
Downloads 0

Compiler assisted parallelization and optimization for multicore architecture

University Birla Institute of Technology and Science Pilani
Year 2014
Downloads 0

Time synchronization and task - assignment algorithms for specific domains of the internet of things

University Birla Institute of Technology and Science Pilani
Year 2019
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Architectures and algorithms for image and video processing using fpga-based platform

University Birla Institute of Technology and Science Pilani
Year 2014
Downloads 0
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Scholarly Publications

E-SATS: An Efficient and Simple Time Synchronization Protocol for Cluster- Based Wireless Sensor Networks

Journal Article
IEEE Sensors Journal. Year: 2019. Volume: 19 , Issue: 21 , Pages: 10144-10156 .
Authors: G. S. S. Chalapathi; Vinay Chamola; S. Gurunarayanan; Biplab Sikdar

An efficient method to compute static single assignment form for multicore architecture

Conference Paper
Year: 2012. Pages: 776-781 .
Authors: D.C. Kiran; S. Gurunaraynan; J.P. Misra; Faizan Khaliq

Fine grain thread scheduling on multicore processors: Cores with multiple functional units

Conference Paper
Year: 2013.
Authors: Munish Bhatia; D. C. Kiran; J. P. Misra; S. Gurunarayanan

Integrated scheduling and register allocation for multicore architecture

Conference Paper
Year: 2013.
Authors: D.C. Kiran; J.P. Misra; D. Yashas; S. Gurunarayanan

Global scheduling heuristics for multicore architecture

Open Access
Journal Article
Scientific Programming. Year: 2015. Volume: 2015 .
Authors: D. C. Kiran; S. Gurunarayanan; Janardan Prasad Misra; Abhijeet Nawal

Register allocation for fine grain threads on multicore processor

Open Access
Journal Article
Journal of King Saud University Computer and Information Sciences. Year: 2017. Volume: 29 , Issue: 1 , Pages: 85-92 .
Authors: D.C. Kiran; S. Gurunarayanan; Janardan P. Misra; Munish Bhatia

Hardware validated efficient and simple Time Synchronization protocol for clustered WSN

Conference Paper
Year: 2016. Pages: 2162-2166 .
Authors: G S S Chalapathi; Raunak Manekar; Vinay Chamola; K.R. Anupama; S Gurunarayanan

Integrated Cooperative Synchronization for Wireless Sensor Networks

Journal Article
IEEE Wireless Communications Letters. Year: 2018. Volume: 8 , Issue: 3 , Pages: 701-704 .
Authors: G. S. S. Chalapathi; Bernhard Etzlinger; S. Gurunarayanan; Andreas Springer
Showing 1 to 8 of 65 publications