Vidwan-ID : 117826

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Personal Details 1
Expertise Details 1
Experience Details 1
Qualification Details 1
Employee ID 0.2
Orcid ID 0.2
Researcher ID 0.2
Scopus ID 0.2
Google Scholar ID 0.2
Honours <=3< /td> 0.3
Honours >3 0.5
Project worth less than Rs.5,00,000/- 0.2
Project worth more than Rs.5,00,000/- 0.5
Membership in professional Bodies < 5 0.5
Membership in professional bodies >=5 1
No of publications <=15 1
No of publications between 15-45 2
No of publications >45 3

Vidwan Score 9

90% Complete
33 Articles
4 Projects

Dr S P Joy Vasantha Rani

Professor
Anna University

Publications

  • 33
    Journal Articles
  • 37
    Conference
    Proceedings
  • 4
    Projects
  • 2
  • 31

Citations / H-Index

137 Citations
7 h-index
81 Citations


Google Scholar


Co-author Network


Expertise

Electrical and Electronic Engineering

Digital VLSI, FPGA designs

Personal Information

Dr S P Joy Vasantha Rani

Female
Department Of Electronics Engineering, Anna University
Chennai, Tamil Nadu, India - 600044


Experience in Months

Academic: 10 Administrative: 0 Industry: 0

Experience

  • Professor

    Department of Electronics Engineering

    Anna University, Chennai

  • Associate Professor

    Anna University, Chennai

  • Assistant Professor - Selection Grade

    Anna University, Chennai

  • Assistant Professor (Senior Grade)

    Anna University, Chennai

  • Assistant Professor

    Anna University, Chennai

  • Teaching Associate

    Anna University, Chennai


Qualification

  • Ph.D

    Madras Institute of Technology, Anna University, Chennai

  • M.E

    College of Engineering, Guindy, Anna University

  • B.E.

    Government College of Engineering, Tirunelveli, Madurai Kamaraj University


Doctoral Theses Guided

2022

AN EFFICIENT FPGA ARCHITECTURE BASED ON HYBRID LOGIC BLOCKS AND PERFORMANCE ENHANCEMENT OF FPGA USING PLACEMENT AND ROUTING ALGORITHMS

Anna University,P.Sudhanya

2020

EMBEDDED EVOLVABLE HARDWARE DESIGN OF DIGITAL CIRCUITS USING BIOINSPIRED ALGORITHMS

Anna University,Ranjith C

2020

DIGITAL PULSE SKIPPING MODULATION STRATEGIES FOR DC DC CONVERTERS TO IMPROVE THE POWER CONVERSION EFFICIENCY AT PARTIALLY LOADED CONDITIONS AND INCORPORATION OF PFC

Anna University,R.Thangam

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2022

AN EFFICIENT FPGA ARCHITECTURE BASED ON HYBRID LOGIC BLOCKS AND PERFORMANCE ENHANCEMENT OF FPGA USING PLACEMENT AND ROUTING ALGORITHMS

Anna University,P.Sudhanya

2020

EMBEDDED EVOLVABLE HARDWARE DESIGN OF DIGITAL CIRCUITS USING BIOINSPIRED ALGORITHMS

Anna University,Ranjith C

2020

DIGITAL PULSE SKIPPING MODULATION STRATEGIES FOR DC DC CONVERTERS TO IMPROVE THE POWER CONVERSION EFFICIENCY AT PARTIALLY LOADED CONDITIONS AND INCORPORATION OF PFC

Anna University,R.Thangam

2019

INTELLIGENT FAULT LOCATION ISOLATION AND SERVICE RESTORATION IN DISTRIBUTION SYSTEM

Anna University,C.Indhumathi

2019

DESIGN OF BUILT IN SELF TEST FOR ANALOG TO DIGITAL CONVERTER WITH STATIC ERROR MODELLING AND CALIBRATION

Anna University,M.Senthil Sivakumar

2018

MULTIPLIERLESS IMPLEMENTATION OF AREA EFFICIENT MULTIRATE FIR FILTER STRUCTURES FOR SAMPLING RATE CONVERSION

Anna University,K.Mariammal

2017

INVESTIGATION OF SWARM INTELLIGENCE TECHNIQUES TO ENHANCE CHANNEL EQUALIZATION

Anna University,D.C.Diana

2017

RECONFIGURABLE AND DEDICATED FIR FILTERS INTERPOLATORS AND MODULATORS FOR SDR

Anna University,S.C.Prasanna

2016

EFFICIENT FIR FILTER ARCHITECTURES FOR MULTICHANNEL FILTERING AND ADAPTIVE FILTERING

Anna University,J.Britto Pari

,

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Membership In Professional Bodies

2025

IEEE

Member

2007

IETE

Life Member

1997

ISTE

Life Member

2025

IEEE

Member

2007

IETE

Life Member

1997

ISTE

Life Member

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Research Projects

Performance Enhancement in FPGA Architecture by Efficient design of logic blocks

Funding Agency : DST - Kiran Division under Women Scientist scheme - A

FPGA based Real-time visual static hand gesture recognition system

Funding Agency : CTDT, Anna University

HER - Harassment Emergency Rescuer

Funding Agency : CTDT, Anna University

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Performance Enhancement in FPGA Architecture by Efficient design of logic blocks

Funding Agency : DST - Kiran Division under Women Scientist scheme - A

FPGA based Real-time visual static hand gesture recognition system

Funding Agency : CTDT, Anna University

HER - Harassment Emergency Rescuer

Funding Agency : CTDT, Anna University

Sounds of Actions - A Technical aid for Speaking Disabled

Funding Agency : CTDT, Anna University

Read Less

Publications (71)