Santanu Sarkar
VIDWAN ID: 94697

Dr Santanu Sarkar

Male Doctor of Philosophy
Assistant Professor | Department of Electronics and Communication Engineering
National Institute of Technology, Rourkela
Expertise: Electrical and Electronic Engineering
25 Publications
2 Projects
148 Scopus Citations
112 CrossRef
12 Years 2 Months Total Experience
Publications
25 Total
Articles
8
Proceedings
17
Activity

No publication activity to display.

Scopus Scopus
148 Citations
9 h-index
CrossRef CrossRef
112 Citations
7 h-index
Google Scholar Google Scholar

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Professional Recognition

National Scholarship For Class 10
1995
MHRD, Govt. of India
Top-9 contestant Cadence Design Contest
2008
Cadence Design Systems, India

Community & Membership

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IEEE
Senior member
Jan 2020

Personal Details

Doctor of Philosophy
2015
N/A
Master of Surgery
2009
N/A
Bachelor of Engineering
2002
National Institute of Cholera and Enteric Diseases
Assistant Professor
Jul 2014 – Present
National Institute of Technology, Rourkela | Department of Electronics and Communication Engineering
Engineering and Technology
Electrical and Electronic Engineering

Related Profiles

Scholarly Work

Development of a Closed-loop Integrated MEMS Capacitive Accelerometer for Inertial and Navigation Systems
Other
Role: Co-Principal Investigator
Intelligent Surveillance Data Retriever (ISDR) for Smart city Applications
Other
Agency: Department of Secondary and Higher Education Role: Co-Principal Investigator
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DISTRIBUTED BINARY CELL REALIZING HYBRID CURRENT STEERING ARCHITECTURE BASED DIGITAL TO ANALOG CONVERTER

IIT Kharagpur
- Application No. : 724/KOL/2013 Filed : 30-11--0001
Published : 30-11--0001 Filed

Personalized Pollution Management (PPM) System

NIT Rourkela
- Application No. : 201931051422 Filed : 30-11--0001
Published : 30-11--0001 Published

Scholarly Publications

An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture

Conference Paper
Year: 2008. Pages: 149-152 .
Authors: Santanu Sarkar; Ravi sankar Prasad; Sanjoy Kumar Dey; Vinay Belde; Swapna Banerjee

An 8-bit 1.8 V 500 MSPS CMOS segmented current steering DAC

Conference Paper
Year: 2009. Pages: 268-273 .
Authors: Santanu Sarkar; Swapna Banerjee

A 10 bit 1 GSPS Nyquist DAC in 180 nm CMOS with high FOM

Journal Article
Analog Integrated Circuits and Signal Processing. Year: 2014. Volume: 80 , Issue: 1 , Pages: 59-68 .
Authors: Santanu Sarkar; Swapna Banerjee

500 MHz differential latched current comparator for calibration of current steering DAC

Conference Paper
Year: 2014. Pages: 309-312 .
Authors: Santanu Sarkar; Swapna Banerjee

An 8-bit low power DAC with re-used distributed binary cells architecture for reconfigurable transmitters

Journal Article
Year: 2014. Volume: 45 , Issue: 6 , Pages: 666-677 .
Authors: Santanu Sarkar; Swapna Banerjee

A 10-Bit 500 MSPS segmented DAC with optimized current sources to avoid mismatch effect

Conference Paper
Year: 2015. Volume: 07-10-July-2015 , Pages: 172-177 .
Authors: Santanu Sarkar; Swapna Banerjee

A 10-bit 500 MSPS segmented DAC with distributed octal biasing scheme

Conference Paper
Year: 2016. Pages: 145-148 .
Authors: Santanu Sarkar; Swapna Banerjee

A 6-Bit 500 MSPS segmented current steering DAC with on-chip high precision current reference

Conference Paper
Year: 2017. Pages: 982-986 .
Authors: Sachin Khandagale; Santanu Sarkar
Showing 1 to 8 of 25 publications