Dr Surajeet Ghosh
Associate Professor
| Department of Computer Science and Technology
INDIAN INSTITUTE OF ENGINEERING SCIENCE AND TECHNOLOGY, SHIBPUR
West Bengal
Expertise:
Computer Science Hardware and Architecture
34
Publications
2
Projects
106
Scopus Citations
102
CrossRef
20 Years 1 Month Total Experience
Scopus
106
Citations
6
h-index
CrossRef
102
Citations
6
h-index
Google Scholar
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Professional Recognition
Gowri Memorial Award (GMA
2008
The Institution of Electronics and Telecommunication Engineers (IETE)
Best Paper Award
2009
International Conference on Advanced Computing (ICAC 09)
Best Paper Award
2013
IEEE International Conference on Computational Intelligence and Computing Research (IEEE ICCIC)
Community & Membership
WBUT Winter School (Under TEQIP Programme), Kolkata
Organising Committee MemberIEEE TENSYMP 2017
Technical Program Committee MemberFifth International Conference on Emerging Applications of Information Technology (EAIT)
International Program CommitteeIEEE International Conference on Computing Methodologies and Communication (ICCMC 2018)
Advisory Committee MemberFourth International Symposium on Signal Processing and Intelligent Recognition Systems (S
Technical Program Committee MemberIEEE Conference on Applied Signal Processing (ASPCON 2018)
Technical Program Committee MemberFifth International Symposium on Signal Processing and Intelligent Recognition Systems (SI
Technical Program Committee MemberIEEE Region 10 Conference (TENCON), Singapore
ReviewerIEEE TENSYMP 2017, Cochin, Kerala
ReviewerFifth International Conference on Emerging Applications of Information Technology (EAIT)
ReviewerIEEE Symposium on Computer Applications&Industrial Electronics (ISCAIE2018), Penang Island
ReviewerFourth International Symposium on Signal Processing and Intelligent Recognition Systems (S
ReviewerIEEE Conference on Applied Signal Processing (ASPCON 2018), Kolkata
Reviewer10th IEEE Control and System Graduate Research Colloquium (IEEE ICSGRC 2019), Malaysia
Reviewer15th IEEE Colloquium on Signal Processing and its Applications (IEEE CSPA 2019), Penang, M
Reviewer4th 2019 IEEE International Conference on Automatic Control and Intelligent Systems (IEEE
Reviewer23rd International Symposium on VLSI Design and Test (VDAT-2019)
ReviewerIEEE International Conference on Advanced Networks and Telecommunications Systems (ANTS)
Session ChairIEEE Region 10 Conference (TENCON), Penang, Malaysia
Session ChairInternational Conference on Computational Intelligence in Pattern Recognition (CIPR), IIES
Session ChairIEEE Computer Society Annual Symposium on VLSI (ISVLSI), Miami, Florida
Session ChairInstitute of Electrical and Electronics Engineers (IEEE)
MemberIEEE Computer Society
MemberIEEE Communications Society
MemberThe Institution of Electronics and Telecommunication Engineers (IETE)
Fellow - Life MemberPersonal Details
Doctor of Philosophy
2017
National Institute of Cholera and Enteric Diseases
Master of Engineering
2005
PIPMATE
Bachelor of Technology
2002
N/A
Associate Professor
Feb 2019 – Present
INDIAN INSTITUTE OF ENGINEERING SCIENCE AND TECHNOLOGY, SHIBPUR
| Department of Computer Science and Technology
Assistant Professor
Sep 2013 – Feb 2019
INDIAN INSTITUTE OF ENGINEERING SCIENCE AND TECHNOLOGY, SHIBPUR
| Department of Computer Science and Technology
Assistant Professor
Apr 2008 – Sep 2013
Maulana Abul Kalam Azad University of Technology, West Bengal
Assistant Professor
Aug 2006 – Mar 2008
Jalpaiguri Govt. Engineering College 101
Engineering and Technology
Scholarly Work
Design and Implementation of a Comparison-Free Scalable High-Throughput Energy-Efficient Hardware Sorting Engine for FPGA-Based Embedded System Applications
CompletedDesign and Implementation of Pipeline Architecture for DNA Sequence Alignment
CompletedDesign of Pipelined Architecture for Biological Sequence Alignment
Intelligent Associative Memory (IAM) System
S. Ghosh
-
Patent No. :
488100
Filed :
23-02-2023
Published :
10-03-2023
Granted
Scholarly Publications
4th generation programmable logic computing: A road map
10.4103/02564602.10876628
Scopus: 3
A scalable high-throughput pipeline architecture for DNA sequence alignment
A fast range matching architecture with unit storage expansion ratio and high memory utilization using SBiCAM for packet classification
10.1109/INDICON.2014.7030357
Scopus: 1
Low-cost hierarchical memory-based pipelined architecture for DNA sequence matching
A novel approach for prefix minimization using Ternary Trie (PMTT) for packet classification
A hierarchical high-throughput and low power architecture for longest prefix matching for packet forwarding
Smart Ternary Content Addressable Memory (STCAM) architecture
10.1109/ICACCCT.2012.6320817
Scopus: 3
Architecture of configurable K-way C-access interleaved memory
10.1109/PACC.2011.5978873
Scopus: 1
Showing 1 to 8 of 34 publications