Janakiraman Viraraghavan
VIDWAN ID: 67635

Dr Janakiraman Viraraghavan

Male Doctor of Philosophy
Assistant Professor | Department of Electrical Engineering
Indian Institute of Technology, Madras
Tamil Nadu
Expertise: Electrical and Electronic Engineering
24 Publications
0 Projects
139 Scopus Citations
114 CrossRef
9 Years 10 Months Total Experience
Publications
24 Total
Articles
14
Proceedings
10
Activity

No publication activity to display.

Scopus Scopus
139 Citations
7 h-index
CrossRef CrossRef
114 Citations
6 h-index
Google Scholar Google Scholar

Loading Scholar statistics...

Professional Recognition

No Data Found

There is currently nothing to display here.

Community & Membership

No Data Found

There is currently nothing to display here.

No Data Found

There is currently nothing to display here.

Personal Details

Doctor of Philosophy
2010
N/A
Assistant Professor
Nov 2016 – Present
Indian Institute of Technology, Madras | Department of Electrical Engineering
Engineering and Technology
Electrical and Electronic Engineering

Related Profiles

Scholarly Work

No Data Found

There is currently nothing to display here.

No Data Found

There is currently nothing to display here.

No Data Found

There is currently nothing to display here.

Scholarly Publications

Voltage and temperature scalable logic cell leakage models considering local variations based on transistor stacks

Journal Article
Journal of Low Power Electronics. Year: 2008. Volume: 4 , Issue: 3 , Pages: 301-319 .
Authors: Janakiraman Viraraghavan; Bharadwaj Amrutur; V. Visvanathan

Voltage and temperature scalable gate delay and slew models including intra-gate variations

Conference Paper
Year: 2008. Pages: 685-690 .
Authors: Bishnu Prasad Das; Janakiraman V. Bharadwaj Amrutur; H.S. Jamadagni; N.V. Arvind

Voltage and temperature scalable standard cell leakage models based on stacks for statistical leakage characterization

Conference Paper
Year: 2008. Pages: 667-672 .
Authors: Janakiraman Viraraghavan; Bishnu Prasad Das; Bharadwaj Amrutur

Voltage and temperature aware statistical leakage analysis framework using artificial neural networks

Journal Article
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Year: 2010. Volume: 29 , Issue: 7 , Pages: 1056-1069 .
Authors: V. Janakiraman; Amrutur Bharadwaj; V. Visvanathan

Statistical compact model extraction: A neural network approach

Journal Article
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Year: 2012. Volume: 31 , Issue: 12 , Pages: 1920-1924 .
Authors: Janakiraman Viraraghavan; Shrinivas J. Pandharpure; Josef Watts

80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory with No Added Process Complexity

Journal Article
IEEE Journal of Solid-State Circuits. Year: 2018. Volume: 53 , Issue: 3 , Pages: 949-960 .
Authors: Balaji Jayaraman; Derek Leu; Janakiraman Viraraghavan; Alberto Cestero; Ming Yin; John Golz; Rajesh Reddy Tummuru; Ramesh Raghavan; Dan Moy; Thejas Kempanna; Faraz Khan; Toshiaki Kirihata; Subramanian S. Iyer

Flash based in-memory multiply-accumulate realisation: A theoretical study

Conference Paper
Year: 2020. Volume: 2020-October .
Authors: S. Ashwin Balagopal; Janakiraman Viraraghavan

A 14 nm 1.1 Mb embedded DRAM macro with 1 ns access

Journal Article
IEEE Journal of Solid-State Circuits. Year: 2016. Volume: 51 , Issue: 1 , Pages: 230-239 .
Showing 1 to 8 of 24 publications