Ministry of Education
Dharmender Nishad
VIDWAN ID: 675129

Dharmender Nishad

Male Doctor of Philosophy
Associate Professor
G. L.BAJAJ INSTITUTE OF TECHNOLOGY AND MANAGEMENT, GREATER NOIDA
Uttar Pradesh
Expertise: Electrical and Electronic Engineering
ORCID 0000-0001-6021-2281 Scopus 57219947399 Google Scholar DGpm3HUAAAAJ
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23 Publications
0 Projects
167 Scopus Citations
145 CrossRef
17 Years 2 Months Total Experience
Publications
23 Total
Articles
14
Proceedings
9
Activity

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Scopus Scopus
167 Citations
8 h-index
CrossRef CrossRef
145 Citations
8 h-index
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Professional Recognition

Awarded Certificate of appreciation for Excellent performance in FDP “A Journey from Blackboard and Beyond
2012
G.L B I T M Gr.Noida

Community & Membership

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ICEIT
Life time
Jan 2010

Personal Details

Doctor of Philosophy
2023
National Institute of Science Technology and Development Studies CSIR
Master of Technology
2009
N/A
Bachelor of Engineering
2006
N/A
Associate Professor
Jul 2009 – Present
G. L.BAJAJ INSTITUTE OF TECHNOLOGY AND MANAGEMENT, GREATER NOIDA
Engineering and Technology
Electrical and Electronic Engineering

Related Profiles

Scholarly Work

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Thermo distance anti-theft device with Person Entry/Exit limitation during the Pandemic

G.L Bajaj Institute of Technology and Management
Gr.Noida
- Patent No. : 46/2021 Filed : 22-04-2021
Published : 12-11-2021 Published

Scholarly Publications

Examination of Interface Trap Charges on Electrically Doped Tunnel FET in the Presence of High-K Dielectric

Conference Paper
Year: 2023. Pages: 1-6 .
Authors: Chandan, B.V.; Dharmender; Subbarao, P.S.; Nigam, K.K.
DOI 10.1109/IEMENTech60402.2023.10423461

Performance Analysis of Double Gated GaAs-Ge Based Hetero Tunnel Field Effect Transistor

Conference Paper
Year: 2020. Pages: 284-287 .
Authors: Dharmender Nishad; Kaushal Nigam; Vinay Anand Tikkiwal; Satyendra Kumar
DOI 10.1109/icsc48311.2020.9182722 Crossref Crossref: 1 Scopus Scopus: 1

Low-K Dielectric Pocket and Workfunction Engineering for DC and Analog/RF Performance Improvement in Dual Material Stack Gate Oxide Double Gate TFET

Journal Article
SILICON. Year: 2020. Volume: 13 , Issue: 7 , Pages: 2347-2356 .
Authors: Dharmender; Kaushal Nigam
DOI 10.1007/s12633-020-00822-6 Crossref Crossref: 35 Scopus Scopus: 37

III-V / Si Heterojunction based Dual Material Stack Gate Oxide TFETs for Low Power Applications

Conference Paper
Year: 2021. Pages: 330-336 .
Authors: Dharmender; Kaushal Nigam; Satyendra Kumar
DOI 10.1109/icsc53193.2021.9673374 Crossref Crossref: 8 Scopus Scopus: 8

Temperature sensitivity analysis of dual material stack gate oxide source dielectric pocket TFET

Journal Article
Journal of Computational Electronics. Year: 2022. Volume: 21 , Issue: 4 , Pages: 802-813 .
Authors: Nigam, K.; Kumar, S.; Dharmender
DOI 10.1007/s10825-022-01902-z Crossref Crossref: 17 Scopus Scopus: 20

Linearity and Harmonic Distortion Performance Assessment of Dual Material Stacked Gate Oxide Source Dielectric Pocket TFET

Conference Paper
Year: 2022. Pages: 130-135 .
Authors: Dharmender; Yadav, P.; Chandel, P.S.; Gupta, N.
DOI 10.1109/SMART55829.2022.10047187 Crossref Crossref: 1 Scopus Scopus: 1

Impact of Interface Trap Charges and Temperature on the Performance of Extended Source Double Gate TFET

Open Access
Other
Year: 2022.
Authors: Dharmender; Nigam, K.; Kumar, S.
DOI 10.21203/rs.3.rs-1762066/v1

Performance assessment of cavity on source dual material split gate GaAs/InAs/Ge junctionless TFET for label-free detection of biomolecules

Journal Article
Applied Physics A. Year: 2022. Volume: 128 , Issue: 10 , Pages: 943 .
Authors: Dharmender; Kaushal Nigam; Satyendra Kumar
DOI 10.1007/s00339-022-06017-7 Crossref Crossref: 13 Scopus Scopus: 16
Showing 1 to 8 of 23 publications