High-K, Gate-Stack Engineered, Junctionless, Nanowire Ferroelectric Field Effect Transistor (J-NW-Fe-Fet) with various catalytic metals for PH3 Sensing Applications
Conference Paper
Year: 2025.
Pages: 401-406
.
Authors: Shalu Garg; Jasdeep Kaur; Anubha Goel; Subhasis Haldar; R. S. Gupta
Demand Side Management Using GUI
Conference Paper
Year: 2019.
Pages: 100-105
.
Authors: Neeraj; Malik, P.; Garg, S.; Singhal, K.
Technology Based Intervention to Improve Social Skills in Students on Autism Spectrum)
Conference Paper
Year: 2019.
Pages: 242-246
.
Authors: Singhal, K.; Neeraj; Garg, S.
Chaotic map based steganography of gray scale images in wavelet domain
Conference Paper
Year: 2014.
Pages: 689-694
.
Authors: Garg, S.; Mathur, M.
Accurate 2-D analytical model for cylindrical gate-junctionless ferroelectric-nanowire (CG-JFe-NW) MOSFET with scaled channel length
Dielectric pocket engineered, gate induced drain leakages (GIDL) and analog performance analysis of dual metal nanowire ferroelectric MOSFET (DPE-DM-NW-Fe FET) as an inverter