Ministry of Education
Nandy S K
VIDWAN ID: 5391

Prof Nandy S K

Male Doctor of Philosophy
Retired Faculty | Computational and Data Sciences
Indian Institute of Science, Bangalore
Karnataka
Expertise: Computer Science Hardware and Architecture
Scopus 7006918597
View older version My Dashboard
183 Publications
0 Projects
1044 Scopus Citations
804 CrossRef
22 Years 7 Months Total Experience
Publications
183 Total
Articles
35
Chapters
1
Proceedings
147
Activity

No publication activity to display.

Scopus Scopus
1,044 Citations
15 h-index
CrossRef CrossRef
804 Citations
14 h-index
Google Scholar Google Scholar

Loading Scholar statistics...

Professional Recognition

No Data Found

There is currently nothing to display here.

Community & Membership

No Data Found

There is currently nothing to display here.

No Data Found

There is currently nothing to display here.

Personal Details

Doctor of Philosophy
1989
Indian Institute of Technology, Delhi
Master of Science
1987
Indian Institute of Technology, Delhi
Bachelor of Engineering
1980
Indian Institute of Technology, Delhi
Bachelor of Science
1977
N/A
Retired Faculty
Jul 2023 – Present
Indian Institute of Science, Bangalore | Computational and Data Sciences
Professor (HAG)
Feb 2004 – Jul 2023
Indian Institute of Science, Bangalore | Computational and Data Sciences
Engineering and Technology
Computer Science Hardware and Architecture

Related Profiles

Scholarly Work

No Data Found

There is currently nothing to display here.

No Data Found

There is currently nothing to display here.

HARDWARE ACCELERATOR FOR ALIGNMENT OF SHORT READS IN SEQUENCING PLATFORMS

INDIAN INSTITUTE OF SCIENCE
Bangalore
Kamataka
IN | INDIAN INST SCIENT
- Patent No. : US20180239864A1 Filed : 30-08-2017
Published : 23-08-2018 Published

DIFFUSION EN CONTINU DE DONNÉES DANS UN ACCÉLÉRATEUR MATÉRIEL POUR LE MAPPAGE ET L'ALIGNEMENT DE LECTURES COURTES | DATA STREAMING IN HARDWARE ACCELERATOR FOR MAPPING AND ALIGNMENT OF SHORT READS

INDIAN INSTITUTE OF SCIENCE
IN
- Patent No. : WO2016139547A1 Filed : 17-02-2016
Published : 09-09-2016 Published

MAPPAGE DE LECTURES COURTES EN SÉQUENÇAGE SUR PLATES-FORMES | MAPPING OF SHORT READS IN SEQUENCING IN PLATFORMS

INDIAN INSTITUTE OF SCIENCE
IN
- Patent No. : WO2016139546A1 Filed : 17-02-2016
Published : 09-09-2016 Published

ACCÉLÉRATEUR MATÉRIEL POUR L'ALIGNEMENT DE LECTURES COURTES DANS DES PLATES-FORMES DE SÉQUENÇAGE | HARDWARE ACCELERATOR FOR ALIGNMENT OF SHORT READS IN SEQUENCING PLATFORMS

INDIAN INSTITUTE OF SCIENCE
IN
- Patent No. : WO2016139545A1 Filed : 17-02-2016
Published : 09-09-2016 Published

MAPPING OF SHORT READS IN SEQUENCING PLATFORMS

Indian Institute of Science
- Patent No. : IN201501089I4 Filed : 05-03-2015
Published : 09-09-2016 Published

DATA STREAMING IN HARDWARE ACCELERATOR FOR ALIGNMENT OF SHORT READS

Indian Institute of Science
- Patent No. : IN201501090I4 Filed : 05-03-2015
Published : 09-09-2016 Published

HARDWARE ACCELERATOR FOR ALIGNMENT OF SHORT READS IN SEQUENCING PLATFORMS

Indian Institute of Science
- Patent No. : IN201501088I4 Filed : 05-03-2015
Published : 05-03-2015 Published

A METHOD AND SYSTEM ON CHIP FABRIC

Indian Institute of Science
IN
- Patent No. : IN200907659P4 Filed : 29-12-2009
Published : 09-07-2010 Published

PROCÉDÉ ET TISSU DE SYSTÈME SUR PUCE | A METHOD AND SYSTEM-ON-CHIP FABRIC

INDIAN INSTITUTE OF SCIENCE
IN | NANDY Soumitra Kumar
IN | NARAYAN Ranjani
IN | VARADARAJAN Keshavan
IN | ALLE Mythri
IN | SATRAWALA Amar Nath
IN | ADARSHA RAO Shimoga Janakiram
IN
- Patent No. : WO2009001368A2 Filed : 28-06-2007
Published : 31-12-2008 Published

MOLECULAR CACHE FOR MULTI-CORE PROCESSORS

INDIAN INSTITUTE OF SCIENCE
- Patent No. : IN256044B Filed : 12-07-2006
Published : 26-04-2013 Published

Scholarly Publications

Geometric Design Rule Check of Vlsi Layouts in Mesh Connected Processors

Open Access
Journal Article
Year: 1994. Volume: 1 , Issue: 2 , Pages: 127-154 .
Authors: S. K. Nandy; R. B. Panwar
DOI 10.1155/1994/96830

TWTXBB: a low latency, high throughput multiplier architecture using a new 4 → 2 compressor

Conference Paper
Year: 1994. Pages: 77-82 .
Scopus Scopus: 6

600MHz half-bit level pipelined multiplier macrocell

Conference Paper
Year: 1994. Pages: 95-100 .
Scopus Scopus: 2

Methodology for architecture synthesis of cascaded IIR filters on TLU FPGAs

Conference Paper
Year: 1994. Pages: 225-228 .
Scopus Scopus: 1

High speed digital filtering on SRAM-based FPGAs

Conference Paper
Year: 1994. Pages: 229-232 .

400 MHz wave-pipelined 8×8-bit multiplier in CMOS technology

Conference Paper
Year: 1993. Pages: 198-201 .

Architectural Synthesis of Computational Engines for Subband Adaptive Filtering

Journal Article
Year: 1999. Volume: 22 , Issue: 3 , Pages: 173-195 .
Scopus Scopus: 2

Computational engine for multirate FIR digital filtering

Journal Article
Signal Processing. Year: 1999. Volume: 79 , Issue: 2 , Pages: 213-222 .
Authors: S Ramanathan; V Visvanathan; S.K Nandy
DOI 10.1016/S0165-1684(99)00095-X Crossref Crossref: 1 Scopus Scopus: 2
Showing 17 to 24 of 183 publications