Ministry of Education
Mahendra Rathor
VIDWAN ID: 514691

Dr Mahendra Rathor

Male Doctor of Philosophy
Assistant Professor | Department of Instrumentation
Devi Ahilya Vishwavidyalaya, Indore
Madhya Pradesh
Expertise: Computer Science Hardware and Architecture
ORCID 0000-0001-8633-7322 Google Scholar cpxEHC0AAAAJ
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48 Publications
0 Projects
386 Scopus Citations
295 CrossRef
6 Years 5 Months Total Experience
Publications
48 Total
Articles
25
Chapters
11
Proceedings
12
Activity

No publication activity to display.

Scopus Scopus
386 Citations
12 h-index
CrossRef CrossRef
295 Citations
9 h-index
Google Scholar Google Scholar

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Professional Recognition

Jay Chaudhry Chair Faculty
2022
IIT-BHU Varanasi
Chairman of IEEE CTSoc MP Chapter
2021
IEEE CTSoc

Community & Membership

IEEE CTSoc Technical committee on Security and Privacy
Member
Jan 2020
IEEE Consumer Technology Society
Member
Jan 2018
IEEE
MEMBER
Jan 2018
ACM
Member
Jan 2024

Personal Details

Doctor of Philosophy
2022
Indian Institute of Technology, Mandi
Master of Engineering
2014
Gujarat Vidyapith, Ahmedabad
Bachelor of Engineering
2012
Gujarat Vidyapith, Ahmedabad
Assistant Professor
Oct 2023 – Present
Devi Ahilya Vishwavidyalaya, Indore | Department of Instrumentation
Faculty
Oct 2022 – Oct 2023
Indian Institute of Technology (Banaras Hindu University), Varanasi
Post-Doctoral Fellow
May 2022 – Oct 2022
Unknown Organization
Adhoc Faculty
Aug 2015 – Aug 2017
Unknown Organization
Engineering and Technology
Computer Science Hardware and Architecture

Related Profiles

Scholarly Work

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SYSTEM AND METHOD FOR EFFICIENT ROUNDING OFF BINARY FLOATING POINT NUMBERS TO NEAREST INTEGERS

1.MAHENDRA RATHOR 2.VISHESH MISHRA 3.URBI CHATTERJEE
- Patent No. : 571538 Filed : 10-04-2023
Published : 20-10-2023 Granted

Scholarly Publications

Improved Delay Estimation Model for Loop Based DSP Cores

Conference Paper
Year: 2019.

Protecting DSP Kernels Using Robust Hologram-Based Obfuscation

Journal Article
IEEE Transactions on Consumer Electronics. Year: 2019. Volume: 65 , Issue: 1 , Pages: 99-108 .
Authors: Anirban Sengupta; Mahendra Rathor
DOI 10.1109/TCE.2018.2885998 Crossref Crossref: 5 Scopus Scopus: 14

Low-Cost Robust Anti-Removal Logic for Protecting Functionally Obfuscated DSP core against Removal Attack

Journal Article
Year: 2019.

Enhanced Functional Obfuscation of DSP core using Flip-Flops and Combinational logic

Conference Paper
Year: 2019.

IP Core Steganography for Protecting DSP Kernels Used in CE Systems

Journal Article
IEEE Transactions on Consumer Electronics. Year: 2019. Volume: 65 , Issue: 4 , Pages: 506-515 .
Authors: Anirban Sengupta; Mahendra Rathor
DOI 10.1109/TCE.2019.2944882 Crossref Crossref: 44 Scopus Scopus: 64

Crypto-Based Dual-Phase Hardware Steganography for Securing IP cores

Journal Article
IEEE Letters of the Computer Society. Year: 2019. Volume: 2 , Issue: 4 , Pages: 32-35 .
Authors: Anirban Sengupta; Mahendra Rathor
DOI 10.1109/LOCS.2019.2942289 Crossref Crossref: 11

Structural Obfuscation and Crypto-Steganography-Based Secured JPEG Compression Hardware for Medical Imaging Systems

Open Access
Journal Article
IEEE Access. Year: 2020. Volume: 8 , Pages: 6543-6565 .
Authors: Anirban Sengupta; Mahendra Rathor
DOI 10.1109/ACCESS.2019.2963711 Crossref Crossref: 29 Scopus Scopus: 29

Security of Functionally Obfuscated DSP cores

Book Chapter
Year: 2020.
Showing 1 to 8 of 48 publications