Shiyamala S
VIDWAN ID: 370994

Dr Shiyamala S

Female Doctor of Philosophy
Assistant Professor | School of Electrical and Communication
Vel Tech Rangarajan Dr. Sagunthala R & D Institute of Science & Technology, Chennai
Tamil Nadu
Expertise: Electrical and Electronic Engineering
45 Publications
0 Projects
79 Scopus Citations
43 CrossRef
11 Years 2 Months Total Experience
Publications
45 Total
Articles
35
Chapters
1
Proceedings
9
Activity

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Scopus Scopus
79 Citations
4 h-index
CrossRef CrossRef
43 Citations
3 h-index
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Personal Details

Doctor of Philosophy
2013
N/A
Assistant Professor
Jul 2015 – Present
Vel Tech Rangarajan Dr. Sagunthala R & D Institute of Science & Technology, Chennai | School of Electrical and Communication
Engineering and Technology
Electrical and Electronic Engineering

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Scholarly Work

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Scholarly Publications

Efficient timing element design featuring low power VLSI applications

Open Access
Journal Article
Year: 2016. Volume: 8 , Issue: 4 , Pages: 1696-1705 .
Authors: Nagarajan, P.; Kavitha, T.; Shiyamala, S.

Designing the antenna for ism band application

Journal Article
Year: 2015.
Authors: Kavitha, T.; Shiyamala, S.; Farithkhan, A.; J.Gnana Arun, J.

A Compact and Power-efficient X-band PLL for High-frequency Wireless Communication in 45 nm CMOS

Open Access
Journal Article
International Research Journal of Multidisciplinary Scope. Year: 2026. Volume: 7 , Issue: 2 , Pages: 37-48 .
Authors: Priya PA; Shiyamala S

A modified map decoder architecture for low power consumption and delay using unfolded technique

Journal Article
Authors: Shiyamala, S.; Kavitha, T.; Nithya Velam, M.

Real-Time Adaptive Rate Control for Hyperspectral Image Compression on FPGA

Open Access
Journal Article
SSRG International Journal of Electrical and Electronics Engineering ( IJEEE ). Year: 2025. Volume: 12 , Issue: 7 , Pages: 238-252 .

Hyperspectral Image Compression Using Lightweight Deep Learning for Onboard UAV Applications

Open Access
Journal Article
International Journal of Electronics and Communication Engineering. Year: 2025. Volume: 12 , Issue: 7 , Pages: 24-34 .

Comparative Analysis of Phase Detector Architectures for High-Speed, Low-Power PLLs in Synopsys 14nm Technology

Conference Paper
Year: 2025. Pages: 33-37 .
Authors: S. Shiyamala; P.A. Priya; P.K. Kowsalya

Phase-Locked Loop Applications: A Comparative Analysis of Charge Pump Topologies

Conference Paper
Year: 2025. Pages: 517-521 .
Authors: S. Shiyamala; P. A. Priya; Hitesh Kumar Reddy; Hemanth Kumar Reddy; Saketh Sai
Showing 1 to 8 of 45 publications