Kunjan D. Shinde
VIDWAN ID: 341581

Dr Kunjan D. Shinde

Male Doctor of Philosophy
Dean
AGM Rural College of Engineering & Technology, VARUR
Karnataka
Expertise: Electrical and Electronic Engineering
21 Publications
5 Projects
106 Scopus Citations
66 CrossRef
10 Years 10 Months Total Experience
Publications
21 Total
Articles
5
Books
4
Chapters
4
Proceedings
8
Activity

No publication activity to display.

Scopus Scopus
106 Citations
7 h-index
CrossRef CrossRef
66 Citations
5 h-index
Google Scholar Google Scholar

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Professional Recognition

Best Paper Award
2020
National conference on Engineering Developments, PESITM, Shivamogga
Interdisciplinary Project - Best Project Award, Project Expo-2026 AGMRCET, Varur
2026
Dept. of BSH, AGMRCET, Varur
Best Project Award- Engineering Exploration
2022
Dr. M S Sheshgiri Campus, KLE Technological University, Hubballi
Best Project Award- Engineering Exploration
2023
Dr. M S Sheshgiri Campus, KLE Technological University, Hubballi
Session Chair
2025
International Conference on Collaborative Informatics 2025 on 17th Dec. 2025 at UBTCE, Davangere, VT
Best Project Award (Secured Second Position
2009
Project Exhibition,KHK institute of Engineering & Technology, Dharwad
Winner - ROBOTICS - LINE FOLLOWER
2011
National Level Technical Fest - PLEIADES, BVBCET, Hubballi
1st Runner UP - ,ROBOTICS - LINE FOLLOWER
2012
National Level Technical Symposium TECHNISIUM’12, SIT Tumkur.

Community & Membership

IEEE
Student Member
Jan 2011
IEEE
(Ph.D.) Graduate Student Member
Jan 2022
ISTE
Student Member
Jan 2009
Research Advisory/ Doctoral Commitee, Research Centers, VTU Belagavi
Member
Jan 2025
IEEE Member
Faculty Advisor, IEEE Student Branach, AGMRCET, varur
Jan 2024
ISTE
Life Member ISTE
Jan 2016
ISTE
Life Member LM114109
Jan 2016
IEEE
Professional Member IEEE - 100111216, Faculty Advisor, IEEE SB AGMRCET
Jan 2025
IEEE
IEEE Student Member - 98195993
Jan 2021
IFERP
Professional member IFERP - PMIN85217934
Jan 2020
IETE
Student Member - SC880744
Jan 2010

Personal Details

Doctor of Philosophy
2023
N/A
Master of Technology
2014
N/A
Bachelor of Engineering
2012
N/A
Dean
Nov 2025 – Present
AGM Rural College of Engineering & Technology, VARUR
Associate Professor
Jul 2024 – —
AGM Rural College of Engineering & Technology, VARUR
Assistant Professor
Oct 2021 – Jun 2024
K L Es College of Engg. & Technology, BELGAUM
Assistant Professor
Jul 2015 – Oct 2021
PES Institute of Technology & Management, SHIVAMOGA
Engineering and Technology
Electrical and Electronic Engineering

Related Profiles

Scholarly Work

One-Day Incubation Program under the RAMP Scheme
Completed
Role: Other
Implementation of Low Cost, Reliable, and Advance Control with Head Movements, Wheelchair for Physically Challenged people
Completed
Role: Other
Head Movement Controlled Wheelchair
Completed
Role: Other
Hardware Efficient VLSI Architecture for Digital Filtering in IOT based Healthcare System
Other
Role: Other
FIR Filter Optimization- Improved Parallel Architecture
Completed
Role: Other
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Scholarly Publications

Impact of VLSI Design Techniques on Implementation of Parallel Prefix Adders

Book
Year: 2018. Pages: 473-482 .
Authors: Shinde, K.D.; Amit Kumar, K.; Shilpa, C.N.

Design of fast and efficient 1-bit full adder and its performance analysis

Conference Paper
Year: 2014. Pages: 1275-1279 .
Authors: Shinde, K.D.; Nidagundi, J.C.

Design and implementation of 1 GHz Current Starved Voltage Controlled Oscillator (VCO) for PLL using 90nm CMOS technology

Conference Paper
Year: 2015. Pages: 335-339 .
Authors: Vishwanath Muddi; Kunjan D. Shinde; Shivaprasad B K

Design and implementation of parallel floating point matrix multiplier for quaternion computation

Conference Paper
Year: 2015. Pages: 289-293 .
Authors: Shivaprasad B K; Kunjan D. Shinde; Vishwanath Muddi

Analysis and comparative study of 8-bit adder for embedded application

Conference Paper
Year: 2015. Pages: 279-283 .
Authors: Kunjan D. Shinde; Sadashiv Badiger

Design and implementation of 1 GHz Current Starved Voltage Controlled Oscillator (VCO) for PLL using 90nm CMOS technology

Conference Paper
Year: 2015.

Design and implementation of parallel floating point matrix multiplier for quaternion computation

Conference Paper
Year: 2015.

Performance analysis and implementation of array multiplier using various full adder designs for DSP applications: A VLSI based approach

Book
Year: 2016. Pages: 731-742 .
Authors: Asha, K.A.; Shinde, K.D.
Showing 1 to 8 of 21 publications