Rohit Singh
VIDWAN ID: 339152

Dr Rohit Singh

Male Doctor of Philosophy
Assistant Professor (Grade-II) | Department of Electronics and Communication Engineering
Dr. B. R. Ambedkar National Institute of Technology, Jalandhar
Punjab
Expertise: Telecommunications
57 Publications
0 Projects
812 Scopus Citations
753 CrossRef
3 Years 9 Months Total Experience
Publications
57 Total
Articles
34
Chapters
2
Proceedings
21
Activity

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Scopus Scopus
812 Citations
13 h-index
CrossRef CrossRef
753 Citations
13 h-index
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IEEE
Member
Jan 2019

Personal Details

Doctor of Philosophy
2021
N/A
Assistant Professor (Grade-II)
Dec 2022 – Present
Dr. B. R. Ambedkar National Institute of Technology, Jalandhar | Department of Electronics and Communication Engineering
Engineering and Technology
Telecommunications

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Scholarly Work

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Scholarly Publications

5G Enabled VANet: Enhancing the Capabilities of Vehicular Communication Network

Conference Paper
Authors: Rohit Singh; Deepak Saluja; Suman Kumar

Design and Comparative Analysis of PN and MOS Varactors for IRS-Enabled Wireless Systems

Conference Paper
Year: 2026.
Authors: Amit Kumar Rana; Mohit Kumar; Ashish Raman; Dinesh Singh; Rohit Singh; Shreya Swaraj

Digital Design of WuR based IoT for Low Power Applications

Conference Paper
Authors: Rangana Bhanu Meher Srinivas; Rohit Singh

FPGA Design of an SNR-Based Adaptive Modulation Selector for 5G/6G Communications

Conference Paper
Authors: Boda Naveen Kumar; Rohit Singh

Modeling and Simulation of a 3×3 Memristor Crossbar Architecture Using the Yakopcic Memristor Model

Conference Paper
Authors: Suraj Prajapati; Bodile Roshan Mukindrao; Rohit Singh

Synergistic Challenges and AI-Enabled Solutions for Integrating Terrestrial and Non-terrestrial Networks

Book Chapter
Year: 2026. Volume: Part F1346 , Pages: 215-226 .
Authors: Shivani Sharma; Rohit Singh; Muhammad Ali Jamshed

Design and Analysis of High Performance MGDI-FS based Brent Kung Adder on the 45nm Technology for Low-Power VLSI Applications

Conference Paper
Authors: Abhishek Kumar; Bodile Roshan Mukindrao; Rohit Singh

Design and Implementation of a Area Efficient Logic BIST Architecture for 4-bit ALU using Verilog and Cadence Genus

Conference Paper
Authors: Akash Kumar Prajapati; Bodile Roshan Mukindrao; Suraj Prajapati; Rohit Singh
Showing 1 to 8 of 57 publications