Karumanchi Dhanumjaya
VIDWAN ID: 327555

Dr Karumanchi Dhanumjaya

Male Doctor of Philosophy
Dean | Department of Electronics and Communication Engineering
Audisankara Deemed to be University
Andhra Pradesh
Expertise: Engineering and Technology
5 Publications
0 Projects
1 Scopus Citations
26 CrossRef
24 Years 11 Months Total Experience
Publications
5 Total
Articles
5
Activity

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Scopus Scopus
1 Citations
1 h-index
CrossRef CrossRef
26 Citations
2 h-index
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Professional Recognition

Best Teacher award
2024
Audisankara College of Engineering & Technology

Community & Membership

Chairman Board of Studies-ECE
Chairman
Sep 2013 – Dec 2022
IETE
Associate Member-212140
Jan 2010
IAENG
MEMBER-109308
Jan 2010
ISTE
LIFE MEMBER
Jan 2009

Personal Details

Doctor of Philosophy
2024
N/A
Master of Technology
2001
N/A
Dean
Sep 2025 – Present
Audisankara Deemed to be University | Department of Electronics and Communication Engineering
Associate Professor
Jul 2006 – Jul 2011
Audisankara Deemed to be University
Assistant Professor
Oct 2001 – Jul 2006
Audisankara Deemed to be University
Head of the Department
Oct 2001 – Sep 2025
Audisankara Deemed to be University | Department of Electronics and Communication Engineering
Engineering and Technology
No Expertise Name

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Scholarly Work

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VLSI ARCHITECTURE FOR HIGH-SPEED DATA ENCRYPTION

Mr. S. Surendra Babu
- Patent No. : 54 Filed : 23-10-2024
Published : 01-11-2024 Published

IOT, AI BASED SMART SOCIAL DISTANCING AND MONITORING ROBOT FOR QUEUE USING MACHINE LEARNING ALGORITHMS

Audisankara College of Engineering & Technology
- Patent No. : 202241023382 Filed : 20-04-2022
Published : 06-05-2022 Filed

Neural Network-Based Image Compression for Edge Devices", Indian Patent no. 202441080841 A, Date of Patent: 01/11/2024

Mr v kiran kumar
- Patent No. : 202441080841 Filed : 30-11--0001
Published : 30-11--0001 Filed

Scholarly Publications

Cell Stability Analysis of Conventional 6T Dynamic 8T SRAM Cell in 45NM Technology

Journal Article
Year: 2012. Volume: 3 , Issue: 2 , Pages: 41-51 .
Authors: K Dhanumjaya

Design and Modeling of Power Efficient, High Performance 32-bit ALU through Advanced HDL Synthesis

Other
Year: 2010. Pages: 13-21 .
Authors: K. Dhanumjaya; G. Kiran Kumar; M. N. Giriprasad; M. Raja Reddy

Design of Low power SRAM in 45nm CMOS Technology

Journal Article

Low Power & Application Specific ALU and its Performance Analysis

Journal Article
Year: 2022.

Low Power Adder Architectures and its Power Analysis using 45 NM CMOS Technology

Journal Article
Year: 2022.