Radha N
VIDWAN ID: 314630

Ms Radha N

Female Doctor of Philosophy
Assistant Professor | Electronics and Communication Engineering
K. Ramakrishnan College of Engineering
Tamil Nadu
Expertise: Telecommunications
23 Publications
0 Projects
99 Scopus Citations
79 CrossRef
12 Years 3 Months Total Experience
Publications
23 Total
Articles
2
Chapters
1
Proceedings
20
Activity

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Scopus Scopus
99 Citations
6 h-index
CrossRef CrossRef
79 Citations
5 h-index
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Personal Details

Doctor of Philosophy
2025
Sultan Qaboos University, Muscat
Master of Engineering
N/A
Assistant Professor
Jun 2014 – Present
K. Ramakrishnan College of Engineering | Electronics and Communication Engineering
Engineering and Technology
Telecommunications

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Scholarly Work

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Scholarly Publications

A Novel Walsh Encoding Scheme for Efficient ATPG in Embedded Processors

Conference Paper
Year: 2025. Pages: 266-272 .
Authors: A. Abinaya; Radha N; S. Rajapriya; Babitha Lincy R; P. Malini; Jency Rubia J

VLSI Architecture for Energy Detection Based Spectrum Sensing

Conference Paper
Year: 2019.
Authors: G. Subhasri; N. Radha

VLSI design of parity check code with hamming code for error detection and correction

Conference Paper
Year: 2019. Pages: 15-20 .
Authors: Subhasri G.; Radha N.

An Efficient Implementation of Decimal Adder Using Parallel Prefix Addition

Conference Paper
Year: 2019. Pages: 587-591 .
Authors: Radha N.; M. Ajeeth; S. Akash; P. Muralikrishnan

A Modified Gate Diffusion Input Technique Based Proficient 4 Bit Priority Encoder

Conference Paper
Year: 2020. Pages: 1024-1026 .
Authors: Radha. N; R. Dagineeshwari; B. Devadharshini

4x4 Multiplier Implementation using Gate Diffusion Input

Conference Paper
Year: 2020. Pages: 960-965 .
Authors: N Shanmuga Priya; N Radha

An Efficient Implementation of FIR Filter Using High Speed Adders for Signal Processing Applications

Conference Paper
Year: 2020. Pages: 1047-1051 .
Authors: S. Akash; M. Ajeeth; N. Radha

Design and Implementation of Primitive Cells, Full Adder, Full Subtractor, and Multiplier using Modified Gate Diffusion Input Logic

Conference Paper
Year: 2020. Pages: 1032-1038 .
Authors: Shanmuga Priya N.; N. Radha
Showing 1 to 8 of 23 publications