Nirmalraj T
VIDWAN ID: 293456

Mr Nirmalraj T

Male Master of Technology
Associate Professor | Department of Electronics and Communication Engineering
Sastra University
TAMILNADU
Expertise: Electrical and Electronic Engineering
13 Publications
0 Projects
48 Scopus Citations
38 CrossRef
18 Years 2 Months Total Experience
Publications
13 Total
Articles
7
Proceedings
6
Activity

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Scopus Scopus
48 Citations
5 h-index
CrossRef CrossRef
38 Citations
4 h-index
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Personal Details

Master of Technology
N/A
Associate Professor
Jul 2008 – Present
Sastra University | Department of Electronics and Communication Engineering
Engineering and Technology
Electrical and Electronic Engineering

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Scholarly Publications

Design of Low-Power 10-Transistor Full Adder Using GDI Technique for Energy-Efficient Arithmetic Applications

Journal Article
Circuits, Systems, and Signal Processing. Year: 2023. Volume: 42 , Issue: 6 , Pages: 3649-3667 .
Authors: T. Nirmalraj; S. K. Pandiyan; Rakesh Kumar Karan; R. Sivaraman; Rengarajan Amirtharajan

Quantum-Inspired Cheetah Optimization Algorithm for Energy-Efficient Cluster Head Selection in Wireless Sensor Networks

Conference Paper
Year: 2026. Pages: 1-6 .
Authors: Thalaimalaichamy M; Nirmalraj T; Radhakrishnan S; Rajendran V. G

Fault Tolerant Carry Save Adders - A NMR Configuration Approach

Conference Paper
Year: 2018. Pages: 210-215 .
Authors: Radhakrishnan, S.; Nirmalraj, T.; Ashwin, S.; Elamaran, V.; Karn, R.K.

New Age Cryptanalysis: Side Channel Attack (SCA) - Investigation of Differential Power Attack on AES-128 Architecture

Conference Paper
Year: 2025.
Authors: Sivaraman R; Mokina Siva Satya Krishna; Vemulapalli Ganesh; D Muralidharan; Radhakrishnan S; Nirmalraj T

Design of Low Power and High Speed MAC based FIR Filter using Hybrid Adder and Modified Booth Multiplier

Conference Paper
Year: 2020.
Authors: S. Radhakrishnan; Rakesh Kumar Karn; Mubarak Ali Meerasha; T. Nirmalraj

Design of low power, high speed PLL frequency synthesizer using dynamic CMOS VLSI technology

Conference Paper
Year: 2018. Pages: 1074-1076 .
Authors: T. Nirmalraj; S. Radhakrishnan; Rakesh Kumar Karn; S.K. Pandiyan

Low latency power aware selfchecking based CSA for sequential multiplier

Conference Paper
Year: 2018. Pages: 1056-1059 .
Authors: S. Radhakrishnan; T. Nirmalraj; Rakesh Kumar Karn; S.K. Pandiyan

An Efficient Design for Area-Efficient Truncated Adaptive Booth Multiplier for Signal Processing Applications

Journal Article
Journal of Circuits, Systems and Computers. Year: 2021. Volume: 30 , Issue: 03 , Pages: 2150037 .
Authors: Radhakrishnan, S.; Karn, Rakesh Kumar; Nirmalraj, T.
Showing 1 to 8 of 13 publications