Ministry of Education
RANJANI ARUNA A
VIDWAN ID: 273161

Dr RANJANI ARUNA A

Female Doctor of Philosophy
Teaching Fellow | Department of Electronics and Communication Engineering
Anna University, Chennai
Tamil Nadu
Expertise: Electrical and Electronic Engineering
ORCID 0000-0002-0956-4668 Scopus 57205492924 ResearcherID rid-0004-0116 Google Scholar SUDpzlEAAAAJ
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7 Publications
0 Projects
13 Scopus Citations
11 CrossRef
12 Years 1 Month Total Experience
Publications
7 Total
Articles
4
Proceedings
3
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Scopus Scopus
13 Citations
2 h-index
CrossRef CrossRef
11 Citations
2 h-index
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Personal Details

Doctor of Philosophy
2023
Sultan Qaboos University, Muscat
Master of Engineering
2014
Xavier Institute of Social Service
Bachelor of Engineering
2011
N/A
Teaching Fellow
Aug 2014 – Present
Anna University, Chennai | Department of Electronics and Communication Engineering
Engineering and Technology
Electrical and Electronic Engineering

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Scholarly Work

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Scholarly Publications

Analysis Optimum Sizing of 12 T PCSA for High Speed Soft Error Tolerant Logic Circuits Design

Journal Article
Journal of Electrical Engineering & Technology. Year: 2022.
Authors: A. Ranjani Aruna; J. Kamala; C. R. S. Hanuman; Dhandapani Vaithiyanathan
DOI 10.1007/s42835-022-01096-1

Implementation of high precision/low latency FP divider using Urdhva–Tiryakbhyam multiplier for SoC applications

Journal Article
Design Automation for Embedded Systems. Year: 2020. Volume: 24 , Issue: 2 , Pages: 111-125 .
Authors: Hanuman, C.R.S.; Kamala, J.; Aruna, A.R.
DOI 10.1007/s10617-019-09225-2 Crossref Crossref: 5 Scopus Scopus: 5

Implementation of multi-precision floating point divider for high speed signal processing applications

Journal Article
The Journal of Supercomputing. Year: 2019. Volume: 75 , Issue: 9 , Pages: 6038-6054 .
Authors: Hanuman, C.R.S.; Kamala, J.; Aruna, A.R.
DOI 10.1007/s11227-019-02902-w Crossref Crossref: 2 Scopus Scopus: 3

Design and optimization of a Bandgap Voltage Reference Circuit

Conference Paper
Year: 2024. Pages: 356-360 .
Authors: A Ranjani Aruna; H Tamil Selvan; J Kamala; C R S Hanuman
DOI 10.1109/SASI-ITE58663.2024.00074 Crossref Crossref: 1 Scopus Scopus: 1

Design of Optimized and Energy Efficient 1-bit Comparator

Conference Paper
Year: 2023.
Authors: Ranjani Aruna A; Kamala J; Sahaana K; Priya M
DOI 10.1109/ICSSES58299.2023.10199595 Crossref Crossref: 1 Scopus Scopus: 2

A novel expeditious switching circuit design for non volatile combinational circuit

Journal Article
Analog Integrated Circuits and Signal Processing. Year: 2022. Volume: 113 , Issue: 3 , Pages: 331-342 .
Authors: A. Ranjani Aruna; J. Kamala; C. R. S. Hanuman
DOI 10.1007/s10470-022-02086-z Crossref Crossref: 2 Scopus Scopus: 2

Design and FPGA Implementation of A Carry - Care Approximate Adder with Reduced Error Probability

Conference Paper
Year: 2026. Pages: 563-568 .
Authors: Aruna A; Ariya Ram S; C.K. Balasundari; Lekha Shree V
DOI 10.1109/ICISS67859.2026.11453622