Kishore Sanapala
VIDWAN ID: 255485

Dr Kishore Sanapala

Male Doctor of Philosophy
Associate Professor | Department of Electronics and Communication Engineering
Marri Laxman Reddy Institute of Technology and Management
Telangana
Expertise: Electrical and Electronic Engineering
16 Publications
0 Projects
236 Scopus Citations
151 CrossRef
12 Years 4 Months Total Experience
Publications
16 Total
Articles
10
Proceedings
6
Activity

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Scopus Scopus
236 Citations
8 h-index
CrossRef CrossRef
151 Citations
6 h-index
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Professional Recognition

Research Award for for the contribution to research through publication in peer reviewed journals and books
2018
VIT-Vellore
VLSID Fellowship
2016
VLSID
BEST PAPER AWARD
2018
•International Conference on Advanced Computing and Big Data Analytics

Community & Membership

International Conference on Innovations in Signal Processing and Embedded Systems
SESSION JUDGE
Jan 2021
IAENG
ENGINEER
Jan 2019
IEEE
Student
Jan 2016

Personal Details

Doctor of Philosophy
2019
N/A
Master of Technology
2014
N/A
Bachelor of Technology
2012
N/A
Associate Professor
Jul 2019 – Present
Marri Laxman Reddy Institute of Technology and Management | Department of Electronics and Communication Engineering
Assistant Professor
Jun 2018 – Jul 2019
Presidency University
Research Associate
May 2015 – Jun 2018
Vellore Institute of Technology, Vellore | School of Electronics Engineering
Assistant Professor
May 2014 – Jun 2015
Avanthi Institute of Engineering and Technology, Chirukupally(V), Bhogapuram(M), Near Tagarapuvalasa Bridge, PIN- 531 162 (CC-Q7)
Engineering and Technology
Electrical and Electronic Engineering

Related Profiles

Scholarly Work

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Scholarly Publications

Parallelisation of machine learning models for credit card fraud detection

Journal Article
International Journal of System of Systems Engineering. Year: 2023. Volume: 13 , Issue: 4 , Pages: 386-406 .
Authors: Banu, J.S.; Thaseen Ikram, S.; Mohanraj, V.; Sanapala, K.; Katina, P.F.

A hadoop based framework integrating machine learning classifiers for anomaly detection in the internet of things

Open Access
Journal Article
Electronics. Year: 2021. Volume: 10 , Issue: 16 , Pages: 1955 .
Authors: Thaseen, I.S.; Mohanraj, V.; Ramachandran, S.; Sanapala, K.; Yeo, S.-S.

Low Power Modulo 2<sup>n</sup>+1 Multiplier Using Data Aware Adder Tree

Open Access
Conference Paper
Procedia Computer Science. Year: 2015. Volume: 70 , Pages: 355-361 .
Authors: Sakthivel, R.; Vanitha, M.; Sanapala, K.; Thirumalesh, K.

Near-zero computing using NCFET for IoT applications

Journal Article
International Journal of Intelligent Enterprise. Year: 2021. Volume: 8 , Issue: 2-3 , Pages: 288-295 .
Authors: Kishore Sanapala; S.V.V. Satyanarayana; R. Sakthivel

Design of Ultralow Voltage-Hybrid Full Adder Circuit Using GLBB Scheme for Energy-Efficient Arithmetic Applications

Conference Paper
Year: 2018. Volume: 471 , Pages: 217-223 .
Authors: Kishore Sanapala; L. Rekha Shree; R. Sakthivel

Two novel subthreshold logic families for area and ultra low-energy efficient applications: DTGDI & SBBGDI

Journal Article
GAZI UNIVERSITY JOURNAL OF SCIENCE. Year: 2017. Volume: 30 , Issue: 4 , Pages: 283-294 .

Low power realization of subthreshold digital logic circuits using body bias technique

Open Access
Journal Article
Indian Journal of Science and Technology. Year: 2016. Volume: 9 , Issue: 5 .
Authors: Kishore Sanapala; R. Sakthivel

Design of full adder using subthreshold DTPT logic

Journal Article
Year: 2016. Volume: 16 , Issue: 1 , Pages: 85-94 .
Showing 1 to 8 of 16 publications