Usha Chennoji
VIDWAN ID: 187828

Mrs Usha Chennoji

Female Doctor of Philosophy
Assistant Professor | Department of Electronics and Communication Engineering
Dayananda Sagar College of Engineering, BANGALORE (2014)
Karnataka
Expertise: Nanoscience and Nanotechnology
16 Publications
1 Projects
138 Scopus Citations
121 CrossRef
7 Years 8 Months Total Experience
Publications
16 Total
Articles
9
Chapters
2
Proceedings
5
Activity

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Scopus Scopus
138 Citations
7 h-index
CrossRef CrossRef
121 Citations
6 h-index
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Professional Recognition

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Community & Membership

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IEEE
Student
Jan 2018
ISTE
Life Member
Jan 2020
IETE
Member
Jan 2020

Personal Details

Doctor of Philosophy
2020
Delhi Institute of Technology and Management
Assistant Professor
Jul 2014 – —
Dayananda Sagar College of Engineering, BANGALORE | Department of Electronics and Communication Engineering
Lecturer
Aug 2005 – Mar 2012
Proudhadevaraya Institute of Technology, Hospete
Engineering and Technology
Nanoscience and Nanotechnology

Related Profiles

Scholarly Work

Analytical Modeling and Simulation of Triple Material Surrounding Gate TFETs
Completed
Agency: Department of Science and Technology Role: Other Grant: SR/WOS-A/ ET-5/2017
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Scholarly Publications

Physics based model for potential distribution and threshold voltage of gate-all-around tunnel field effect transistor (GAA-TFET)

Conference Paper
Materials Today: Proceedings. Year: 2019. Volume: 45 , Pages: 4052-4057 .
Authors: C. Usha; P. Vimala; V.N. Ramakrishnan

Analytical drain current model for fully depleted surrounding gate TFET

Journal Article
Journal of Nano Research. Year: 2018. Volume: 55 , Pages: 75-81 .
Authors: C. Usha; Palanichamy Vimala

A tunneling FET exploiting in various structures and different models: A review

Conference Paper
Year: 2015.
Authors: C. Usha; P. Vimala

Impact Analysis and Simulation of Cylindrical Nanowire Biosensor

Conference Paper
Year: 2021. Pages: 285-288 .
Authors: K Darshan; Tarun Chaudhary; Kadam Yashwant; P. Vimala; Kumar Sushant Ranjan; C Usha

Impact of material in gate engineering of various TFET architectures

Book Chapter
Year: 2024. Pages: 333-351 .
Authors: P. Vimala; C. Usha

Evolution of Heterojunction Tunnel Field Effect Transistor and its Advantages

Book Chapter
Year: 2023. Pages: 99-123 .
Authors: C. Usha; P. Vimala

A Study of Graphene FET for Better Performance

Conference Paper
Year: 2023.
Authors: P. Vimala; Dharshan K; Murthy; Harshith S; Kishore V M; C. Usha

Modeling of Source Pocket Engineered PNPN Tunnel FET on High-K Buried Oxide (H-BOX) Substrate for Improved ON Current

Journal Article
SILICON. Year: 2022. Volume: 14 , Issue: 16 , Pages: 10383-10389 .
Authors: P. Vimala; Mahboob ul Haque; C. Usha
Showing 1 to 8 of 16 publications