BHARAT CHOUDHARY
VIDWAN ID: 174185

Dr BHARAT CHOUDHARY

Male Doctor of Philosophy
Assistant Professor | Department of Electronics and Communication Engineering
Malviya National Institute of Technology, Jaipur
Rajasthan
Expertise: Agronomy
34 Publications
0 Projects
225 Scopus Citations
170 CrossRef
10 Years 9 Months Total Experience
Publications
34 Total
Articles
21
Proceedings
13
Activity

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Scopus Scopus
225 Citations
8 h-index
CrossRef CrossRef
170 Citations
7 h-index
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Professional Recognition

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Community & Membership

IEEE Rajasthan SubSection
Executive Member
Jan 2022
IEEE
Senior Member
Jan 2021

Personal Details

Doctor of Philosophy
2018
Government Post Graduate College, Ambala Cantt.
Master of Technology
2013
Government Post Graduate College, Ambala Cantt.
Bachelor of Technology
2010
National Institute of Technology, Uttarakhand
Assistant Professor
Feb 2020 – Present
Malviya National Institute of Technology, Jaipur | Department of Electronics and Communication Engineering
Deputy Director
Dec 2018 – Feb 2020
Ministry of Defence Government of India
Assistant Director
Jan 2017 – Dec 2018
Ministry of Defence Government of India
Assistant Manager
Dec 2015 – Jan 2017
Ministry of Defence Government of India
Agricultural Sciences
Agronomy

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Scholarly Work

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Scholarly Publications

Optimization in PFSCL Design Using Floating-Gate MOSFET

Conference Paper
Year: 2023. Pages: 281-286 .
Authors: Ruchi Bhaskar; Bharat Choudhary; Rajesh Saha

Unveiling the impact of ITCs on High-k SOI GaN FinFET and its sensitivity analysis for improved reliability: a simulation study

Journal Article
Analog Integrated Circuits and Signal Processing. Year: 2026. Volume: 128 , Issue: 1 .
Authors: Vandana Singh Rajawat; Bharat Choudhary; Ajay Kumar

NQS Small-Signal Circuit Modelling of GaN-SOI-FinFET for RF/Wireless Applications

Journal Article
Circuits, Systems, and Signal Processing. Year: 2025. Volume: 44 , Issue: 8 , Pages: 5455-5474 .
Authors: Vandana Singh Rajawat; Bharat Choudhary; Ajay Kumar

Development of Generic Custom FILL Parameterized Cell

Conference Paper
Year: 2025. Pages: 562-567 .
Authors: Tanu Shree Gothwal; Bharat Choudhary; Dheeraj Singh Rajpiut

Design and Analysis of a GHz PLL Using GDI and Pass Transistor Based PFD with a Lock Time of 520 ns

Conference Paper
Year: 2025. Pages: 243-248 .
Authors: Dheeraj Singh Rajput; Bharat Choudhary; Archana Singhal; D. Boolchandani

An efficient race-free dynamic MCML design for multistage applications

Journal Article
Analog Integrated Circuits and Signal Processing. Year: 2026. Volume: 126 , Issue: 1 .
Authors: Dheeraj Singh Rajput; Bharat Choudhary; Dharmendar Boolchandani; Archana Singhal

A Low-Phase Noise, Low-Power PFD Circuit Using GDI and Pass Transistor Logic with PVT tolerance

Conference Paper
Year: 2026.
Authors: Dheeraj Singh Rajput; Bharat Choudhary; Archana Singhal; D. Boolchandani

Design and optimization of a Quad-Tail-Cell dynamic MCML for low-power three-input logic using Taguchi and ANOVA methods

Journal Article
Analog Integrated Circuits and Signal Processing. Year: 2026. Volume: 126 , Issue: 1 .
Authors: Dheeraj Singh Rajput; Bharat Choudhary; Dharmendar Boolchandani
Showing 1 to 8 of 34 publications